Abstract: A negative resist composition including a polymeric matrix material, a polymerizable monomer, and an onium salt radiation sensitive initiator. The monomer is polymerized by irradiating the resist with an e-beam, x-ray, or ultraviolet source and heating the exposed resist. The resist is developed by a dry etchant such as plasma or a reactive ion etchant.

Abstract: An electrode and substrate assembly for a plasma reactor allows high power plasma processing with low frequency excitation. The electrode sub-assembly is contained in a chamber which is used for pre-treatment such as de-scumming photoresist or for post-etch resist stripping and passivation. A post-etch treatment is essential in plasma aluminum etching.

Abstract: A low particulate vacuum chamber semiconductor wafer input/output valve minimizes the particulate generation by taking advantage of a camming motion at the instant of closing to insure that the valve closes normal to the reaction chamber wall. This eliminates any friction between a glandular seal in the vacuum chamber wall. As the valve closes, it strikes a stop which causes a 90 degree change in direction of the valve forcing it into tape cut. This change of direction is accomplished through a combination of an upper motion of a backing plate, and a spring-loaded linkage in stock. As the gate closes there is some particulte generated at the interface of the valve plate and the stop. This is handled by placing the area of contact outside the transportation path for the semiconductor wafer.

Abstract: A plasma reactor for the manufacturing of semiconductor devices has powered loadlocks and a main process chamber where slices can be processed one slice at a time with pre-etch plasma treatments before the main etching processing and afterwards receive a post etch treatment. The system comprises powered loadlocks, a main chamber, vacuum pumps radio frequency power supplier, radio frequency matching networks, heat exchangers and throttle valve and pressure controllers, gas flow distribution and microprocessor controllers. The semiconductor wafers are automatically fed one at a time from storage cassettes through isolation gates with articulated mechanical arms to a powered entry loadlock for pre-etching processes. At the completion of the pre-etching processing, the semiconductor wafer is transferred to the main chamber automatically for the main etch process and then to the powered exit loadlock for post etch treatment and finally to an output cassette.

Abstract: A monolithic low noise variable gain amplifier with series feedback includes a dual gate field effect transistor (DGFET) having a common source FET and a common gate FET with scaled gate widths and/or an interelectrode matching element connected to ground through a capacitor positioned between the two gates for reducing the minimum noise figure of the common gate FET and establishing the output load for the common source FET, and an inductive series feedback line for connecting the common source FET to ground. The amount of series feedback between the source and ground of the DGFET as well as the appropriate output load obtained through gate width scaling are selected to make the conjugate input impedance equal to the optimum impedance for a simultaneous noise match and power match.

Abstract: Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact.

Abstract: A substrate to use as electrode in a plasma etch reactor is fabricated from aluminum with an annulus that is anodized to protect it from being exposed to the plasma.

Abstract: A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.

Abstract: The disclosure relates to a charge imaging matrix wherein the floating gate level closest to the substrate is used as a storage gate and the second floating gate level is used as both a field plate and a transfer gate due to the formation of a step in the insulator thereunder which leaves an N-channel in the transfer region when the remainder of the gate is biased to flat band.

Abstract: Electron detector apparatus and method for detecting secondary electrons released from a body, of particular utility in testing integrated circuits in an operational state. The apparatus utilizes a magnetic lens having an axis of symmetry, for producing a magnetic field that progressively weakens along the axis, so that the secondary electrons travel through the magnetic lens in progressively elongated helical paths and approach an electron retarding means, for example a planar grid, at approach angles to the direction of the axis such that their approach speeds along the axis are substantially equal to their actual speeds. The secondary electrons are collected after passage through the retarding means.

Abstract: A semiconductor read/write memory device of the type using dynamic one-transistor storage cells employs dummy capacitors which are the same size as the storage capacitors, and these dummy capacitors are precharged to a reference voltage level less than half the supply voltage. A voltage divider sets the precharge level, but this divider is shunted by a control device initially so the dummy capacitors are quickly discharged to the reference level. A comparator with differential inputs determines when the reference level has reached the proper value, then the control device and the comparator are shut off to reduce power, and the reference level maintained by the voltage divider. The dummy capacitor precharge starts during the later part of an active cycle, so the specified cycle time can be minimized.

Abstract: Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This process is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The process avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with the ion implant method, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

Abstract: A video memory controller controls a DRAM (dynamic random access memory) used as a video memory and as a system memory. The video memory and the video memory controller are normally a part of a video system which includes a data processor, the video memory, the video memory controller, a CRT controller and a CRT display device. The video memory controller includes a row address latch for storing a row address from the data processor, a column address latch for storing a column address from the data processor, a refresh address register for storing a memory refresh address and a display update generator for sequentially generating the addresses necessary for update of the CRT display. A multiplexer couples the proper address to the video memory under control of a memory cycle generator which generates the timing of the memory refresh and display update. An arbiter device enables only one of the possible memory cycles at a time.

Abstract: A logic unit used as the basic building block in a bipolar integrated circuit is formed in a rectangular oxide-isolated island wherein thick oxide walls at one end of the island define three of four edges of a P-type region which serves both as the base of an NPN drive transistor and the emitter of a PNP clamp transistor. An input contact to the logic unit is disposed on the upper semiconductor surface of the island in ohmic contact with the common P-type region. The input contact extends across the entire width of the island to minimize the base resistance of the drive transistor and thus increase the switching speed of the logic unit.

Abstract: A color CCD imager with three correlated clamp-sample-and-hold sense amplifiers (one for each color channel). The three control lines necessary to operate this type of amplifier, together with the clock lines necessary for the three shift registers which feed them, are all wired together, so that correct phasing of the three outputs is maintained with only three clock lines.

Abstract: A generator circuit for producing a negative bias voltage on a substrate for a semiconductor device employs a multistage on-chip oscillator driving individul charge pump circuits for each stage. The oscillator may produce a frequency related to the value of the negative bias, using a feedback circuit. Each of the charge pump circuits includes a capacitor and an MOS diode coupled to the substrate and another diode coupled to the ground terminal of the supply.

Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit lines, and active pull-up circuits for restoring bit lines to a full 1 level. The pull-up circuits are not activated on the dummy cell sides, however, because the power used to restore the dummy cell would be wasted since the dummy cell capacitors are always discharged. The device illustrated uses folded bit lines and multiplexed sense amplifiers; one of two opposite pairs of bit lines is selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. The multiplex circuitry selects one side or the other for sensing, and also couples precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other.

Abstract: A video system is able to change the display on a video monitor with a minimal number of memory transfer cycles. The video system includes a monitor for displaying of processed data, a processor means for processing the data to be displayed, a display memory means divided into a plurality of planes addressable by a row address, the display memory stores the data that has been processed by the processor means. There are additional other sources of data which is processed by the processor means for storing in the display memory and subsequently being displayed by the CRT monitor . A control means controls the data transfer between the data sources, the processor, the display memories, and the CRT monitor and includes a row address override circuit. The row address override circuit comprises a plurality of output logic for providing a write enable signal to a memory plane. Each memory plane is connected to a cross finding output logic circuit.

Abstract: A high speed computer system has a high speed processor for executing program sequences in a single fetch cycle; an instruction memory means for communicating with the high speed processor; a data memory for communicating with the high speed processor and a special subroutine handling operation which is implemented through a picosequencer which provides for interrupting the program, loading the contents of the instructions being implemented into a memory, executing the subroutine under the control of a picosequencer and then returning to the operation of the program.

Abstract: A portable educational device that is adapted to be used in conjunction with a counter (12) having a display (14) and a keyboard (16) for input of data. A memory slot (18) or an alternate port (19) is provided on the computer (12) to receive the educational device (20). Educational device (20) contains a keypad (24) and a display (26) and operates independent of the computer (12). The educational device (20) includes a central processing unit (48), a Read Only Memory (42) and a Random Access Memory (44). A primary power source (54) supplies power to the educational device (20) during the operation thereof. A back-up power source (56) provides power to the Random Access Memory (44) to form a non-volatile memory for retention of data during periods of non-use. A connector (34) interfaces with the computer (12) to allow the computer (12) to address the Random Access Memory (44) to retrieve data stored therein and to store data at selected locations therein for use by the Central Processing Unit.