Patents Assigned to Texas Instruments
-
Patent number: 8792650Abstract: A driver circuit includes a first driver amplifier that is configured to generate a first output in response to a first reference voltage input and a first audio input; a second driver amplifier that is configured to generate a second output in response to the first reference voltage and a second audio input; and a common mode (CM) amplifier, coupled to the first driver amplifier and the second driver amplifier. The CM amplifier is configured to generate an output in response to a second reference voltage input, the first reference voltage input being a divided version of the output. Gains of the first driver amplifier, second driver amplifier and the CM amplifier are equal. Noise at the output appears across a plurality of resistors coupled at the outputs of the first driver amplifier, second driver amplifier and the CM amplifier and cancels with respect to the output of the CM amplifier.Type: GrantFiled: June 10, 2011Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Vineet Mishra
-
Patent number: 8792288Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.Type: GrantFiled: January 30, 2013Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporationInventors: Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 8789705Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.Type: GrantFiled: December 14, 2010Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: James Cooper Wainerdi, Robert Reid Doering, Luigi Colombo
-
Patent number: 8793485Abstract: A system can comprise a memory to store computer readable instructions and a processing unit to access the memory and to execute the computer readable instructions. The computer readable instructions can comprise a certificate manager configured to request generation of N number of random values, where N is an integer greater than or equal to one. The certificate manager can also be configured to request a digital certificate from at least one certificate authority of at least two different certificate authorities. The request can include a given one of the N number of random values. The certificate manager can also be configured to generate a private key of a public-private key pair, wherein the private key is generated based on a private key of each of the least two certificate authorities.Type: GrantFiled: December 15, 2011Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Eric Thierry Peeters
-
Patent number: 8791012Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.Type: GrantFiled: March 21, 2007Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Stanford Joseph Gautier, Jr., Rabah Mezenner, Randy Long
-
Patent number: 8791845Abstract: A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref/2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.Type: GrantFiled: August 31, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Gautam S. Nandi, Rishubh Khurana
-
Patent number: 8791527Abstract: An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.Type: GrantFiled: April 23, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Gregory Charles Baldwin
-
Patent number: 8792179Abstract: A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method of forming and utilizing a package that exposes regions of an alignment reference plane. The device within the package is mounted on the reference plane such that the exposed regions allow precise alignment with the device in a direction perpendicular to the reference plane. Alignment surfaces formed in a display system or other system contact the reference plane at the exposed regions to position the packaged device relative to other components of the system. One embodiment of the package 400 taught has laminated layers forming the package substrate 402 and providing a precision reference plane 416 relative to the position of the micromirror device 404. The package may be formed by laminating several layers of material in sheets to form several package substrates simultaneously.Type: GrantFiled: November 12, 2010Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Joshua J. Malone
-
Patent number: 8790981Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.Type: GrantFiled: August 5, 2009Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Byron Neville Burgess, Sameer P. Pendharkar
-
Patent number: 8792421Abstract: A novel and useful apparatus for and method of Improving idle connection state power consumption in wireless local area network (WLAN) system. Beacon transmission delay information is determined by the access points and advertised to the stations via a Beacon Transmission Delay Information Element. In response, the stations adjust their Wake For Beacon Reception time accordingly to wake up at a time much closer to the actual receipt of the Beacon, thereby reducing power consumption due to the reduced time the receive circuits need to be powered on.Type: GrantFiled: March 9, 2011Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventor: Artur Zaks
-
Patent number: 8792567Abstract: A method of powerline communications between a plurality of nodes on a powerline communications (PLC) channel including a first node and a second node. At least one communication quality measure is determined for the PLC channel. Based on the communication quality measure, a preamble of a data frame is dynamically switched between a reference preamble having a reference symbol length including a reference number of syncP symbols and a reference number of syncM symbols and at least a first extended preamble having an extended symbol length that is greater than (>) the reference symbol length. The data frame is then transmitted on the PLC channel.Type: GrantFiled: June 18, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Anand G. Dabak, Tarkesh Pande, Il Han Kim, Ramanuja Vedantham, Kumaran Vijayasankar, Gang Xu
-
Patent number: 8792377Abstract: A transport block size (TBS) of a first uplink message (RACH Msg3) transmitted on a Physical Uplink Shared Channel (PUSCH) during a random access procedure in a User Equipment (UE) accessing a radio access network may be determined by receiving a pathloss threshold parameter. A downlink pathloss value indicative of radio link conditions between the UE and a base station (eNB) serving the UE is then determined. A smaller value of TBS is selected from a set of TBS values if the determined pathloss value is greater than an operating power level of the UE minus the pathloss threshold parameter. A larger value of TBS is selected if the pathloss value is less than the operating power level of the UE minus the pathloss threshold parameter and the TBS required to transmit the RACH Msg3 exceeds the smaller TBS value.Type: GrantFiled: March 6, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Pierre Bertrand, Shantanu Kangude, Zukang Shen
-
Publication number: 20140208176Abstract: In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where the scan input is of pull-up logic in functional mode. The input circuit includes a first pull-up path comprising a switch receiving data input and a switch receiving scan enable input, and second pull-up path comprising a switch receiving scan input, first pull-down path comprising a switch receiving the scan enable input and a switch receiving the scan input, and second pull-down path comprising a switch receiving the data input. The storage element includes a shifting circuit configured to provide a second signal in response to the first signal at second node, and a scan output buffer coupled to the second node and configured to provide a scan output at a scan output terminal in response to the second signal.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: Texas Instruments IncorporatedInventors: Naishad Narendra Parikh, Pranjal Tiwari, Aishwarya Dubey
-
Publication number: 20140208177Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.Type: ApplicationFiled: January 24, 2013Publication date: July 24, 2014Applicant: Texas Instruments IncorporatedInventors: Rubin Ajit Parekhji, Srivaths Ravi, Prakash Narayanan, Milan Shetty
-
Patent number: 8786338Abstract: A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse.Type: GrantFiled: November 14, 2011Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Vijay B. Rentala, Srinath M. Ramaswamy, Brian P. Ginsburg, Eunyoung Seok, Baher S. Haroun
-
Patent number: 8787404Abstract: A method of communicating in a network having a plurality of nodes including a base node (BN), and a plurality of service nodes (SNs) having at least one switch node (SW) and at least one terminal node (TN). The method includes at least one of a) a first SN from the plurality of SNs receiving (i) a data/ALV_B/ACK frame from the BN or (ii) a beacon from the BN or SW, and restarting a first KA timer at the first SN upon (i) or (ii), and b) restarting an ALV_S timer at the BN for the first SN upon receiving a data/ALV_S/ACK frame from the first SN.Type: GrantFiled: May 16, 2012Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Kumaran Vijayasankar, Ramanuja Vedantham, Xiaolin Lu
-
Patent number: 8787403Abstract: A system includes a controller that provides an output control signal based on two or more control inputs. The controller determines an indication of radio frequency (RF) bandwidth availability based on a given one of the control inputs. The output control signal can correspond to the RF bandwidth availability and status of at least one other wireless condition affecting RF bandwidth. An audio quality adjuster can adjust quality parameters used to encode an audio stream for one or more audio sinks based on the output control signal.Type: GrantFiled: May 14, 2012Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Yonathan Shavit, Alon Paycher, Yaniv Rabin, Dotan Ziv
-
Patent number: 8787195Abstract: Systems and methods for beacon selection in communication networks are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include performing, using a terminal device deployed in a communications network, receiving a beacon transmitted by a switch device within the communications network and, in response to the terminal device having had a previous connection with the switch device, determining a connection time of the previous connection. The method may also include performing at least one of: adding the switch device to a blacklist in response to the connection time being smaller than a first threshold value, or selecting the switch device for subsequent communication in response to the connection time being greater than a second threshold value.Type: GrantFiled: June 22, 2012Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Kumaran Vijayasankar, Ramanuja Vedantham, Robert Liang, Susan Yim, Xiaolin Lu
-
Patent number: 8787477Abstract: Embodiments of the invention provide a methods for the assignment of codewords to the available constellation points to minimize the Hamming distance between adjacent codewords. An hexagonal constellation is modeled as a two-dimensional trellis with an horizontal axis varying across a plurality of constellation points and a vertical axis varying across a plurality of codewords [0, 1, . . . , N?1]. A best path through the trellis is found to select a single constellation point per each codeword where a codeword is to be assigned. A each state in the transition across the trellis diagram, a current score and the best path that leads to the state is stored in a memory. Each codeword is assigned to the selected constellation point. The hexagonal constellation is used for transmitting data in a communication system.Type: GrantFiled: September 18, 2013Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Mohamed Farouk Mansour, Srinath Hosur, JuneChul Roh
-
Patent number: 8787594Abstract: A volume level and crossfade controller with programmable fades and audio stream priority controls saturation for a multiple audio stream mixer. Start of fade and end of fade events trigger updates of relative volume level targets and volume ramps.Type: GrantFiled: January 30, 2006Date of Patent: July 22, 2014Assignee: Texas Instruments IncorporatedInventors: Stephen J. Fedigan, Daniel S. Jochalson, Jason D. Kridner, Jeffrey S. Hayes