Abstract: By a medical implant transceiver implantable within a body of a living organism, a portion of a signal is received from a medical controller transceiver external to the body of the living organism. Based on directions within the portion of the signal, a time duration is determined, after which a subsequent portion of the signal is to be transmitted from the medical controller transceiver. The directions include a value indicative of the time duration. The time duration differs based on the value. The subsequent portion is to be transmitted from the medical controller transceiver after an end of the portion. The medical implant transceiver enters into an inactive state for the time duration and awakens after the time duration has elapsed.

Abstract: In an embodiment of the invention, the voice coil of an electro dynamic transducer is protected against thermal overload by estimating the temperature of a magnet in the electro dynamic transducer. When a power limit based on the temperature of the magnet and on a predetermined voice coil temperature limit is reached by an audio signal, the power applied to the voice coil is reduced.

Abstract: A digital control circuit is provided for use with a switch-mode power converter that receives an input signal at a first input node and a control signal at a second input node, and that provides an output signal at a first output node and a current signal at a second output node. The digital control circuit generates a programmable current reference signal based on a difference between the output signal and a voltage reference signal, calculates a time instant when the current signal substantially equals the programmable reference current signal, and generates the control signal based on the calculated time instant.

Abstract: A communication unit has BT and LTE transceivers, and a BT processor. The BT processor sets up a BT connection over the BT transceiver; performs a legacy command to synchronize BT transactions over the BT connection based on LTE frames in a LTE connection over the LTE transceiver, so that a BT network clock is synchronized to LTE frames. The legacy command is a role switch command that is used to set a BT alignment time of a switch point between Bluetooth master/slave packets to a LTE switch between transmit and receive; and is specified in a BT Core Specification 4.0 or earlier. The processor can determine an expected alignment time to align BT master and slave packets to transmit and receive in the LTE frame based on a start time of the LTE frame, and can indicate the expected alignment time in the legacy command.

Abstract: An electronic circuit including a bus (3521), a peripheral (3510.i/3552.1) coupled to the bus (3521), the peripheral having a storing circuit (3620.i, 3625.i) for a succession-presetting and a parameter setting currently-effective for peripheral operation on the bus (3521); and a power management circuit (3570) operable in response to a power management transition request (GO_bit) to send a first signal (START_bit_i) to the peripheral, and to initiate a bus frequency transition, and to send a second signal (PER_ENABLE_i) to the peripheral after the bus frequency transition; and the peripheral is responsive to the first signal (START_bit_i) to stall peripheral operation on the bus (3521), the peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on the bus (3521) are stalled and responsive to the second signal (PER_ENABLE_i) to re-enable peripheral operation on the bus (3521).

Abstract: A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to primary node in a wireless network is obtained using an orthogonal covering sequence and a second sequence. Embodiments of the present invention mitigate interference by calculating a first orthogonal covering (OC) index and a second OC index from an indicator received from a serving base station (NodeB). A first index n1 is derived and a second index n2 is derived using the first index n1. A first orthogonal covering (OC) index and a first cyclic shift (CS) is determined using the derived index n1. A second OC and a second CS is derived using the derived index n2. A first slot of a subframe is generated using the OC indexed by the first OC index and the first CS and a second slot of the subframe is generated using the OC indexed by the second OC index and the second CS.

Abstract: A method for generating an output voltage from an input voltage with a switched mode power supply at a switching frequency is provided. At the switching frequency, a transistor within a switching circuit is deactivated so as to enter into a dead time interval, where the switching circuit includes a switching node. A negative inductor current is used during the dead time interval so as to slew the switching node, where switching frequency and the input voltage are sufficiently large so as to overcome a loss incurred by using the negative inductor current.

Abstract: A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Abstract: A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region.

Abstract: Dynamically reducing power consumption by a processor in a computer system by determining a maximum number of times (token count) that the processor can incur a start-up delay after being placed into a low-power mode during a token period of time when executing a task for a token period of time. The processor may be placed into the low-power mode while executing the task in response to an idle indicator only if a current value of the token count assigned to the task is greater than zero. The current value of the token count is decremented each time the processor incurs a start-up delay in response to being awakened from the low-power mode. The current token count is reset to match the assigned token count at the end of each token period. Furthermore, wakeup may be anticipated to allow the processor to be awakened preemptively.

Abstract: Transmission of random access preamble structures within a cellular wireless network is based on the use of cyclic shifted constant amplitude zero autocorrelation (“CAZAC”) sequences to generate the random access preamble signal. A pre-defined set of sequences is arranged in a specific order. Within the predefined set of sequences is an ordered group of sequences that is a proper subset of the pre-defined set of sequences. Within a given cell, up to 64 sequences may need to be signaled. In order to minimize the associated overhead due to signaling multiple sequences, only one logical index is transmitted by a base station serving the cell and a user equipment within the cell derives the subsequent indexes according to the pre-defined ordering. Each sequence has a unique logical index. The ordering of sequences is identified by the logical indexes of the sequences, with each logical index uniquely mapped to a generating index.

Abstract: The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor coupled to an address bus; a cache memory that couples to the address bus and comprises cache data (the cache memory divided into a plurality of ways); and a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index. The processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.

Abstract: System and method for a full featured network communications protocol that is both memory and processor efficient. A preferred embodiment comprises a method for transmitting information between electronic devices, the method comprising creating a connection between a pair of electronic devices, sending a packet between the pair, acknowledging a receipt of the packet by a receiver of the packet, and dissolving the connection when it is no longer needed. The creating of the connection comprises assigning a port number to the connection at an initiating electronic device and then transmitting a connection request containing the port number to a servicing electronic device. After the transmitting, the creating further comprises receiving a second port number to the connection from the servicing electronic device.

Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.

Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage, and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block.

Abstract: A method for encoding a video sequence in a scalable video encoder to generate a scalable bitstream is provided that includes encoding the video sequence in a first layer encoder of the scalable video encoder to generate a first sub-bitstream, encoding the video sequence in a second layer encoder of the scalable video encoder to generate a second sub-bitstream, wherein portions of the video sequence being encoded in the second layer encoder are predicted using reference portions of the video sequence encoded in the first layer encoder, combining the first sub-bitstream and the second sub-bitstream in the scalable bitstream, and signaling an indication of a highest temporal level of the first sub-bitstream comprising at least one of the reference portions in the scalable bitstream.