Abstract: A method for encoding a video sequence in a scalable video encoder to generate a scalable bitstream is provided that includes encoding the video sequence in a first layer encoder of the scalable video encoder to generate a first sub-bitstream, encoding the video sequence in a second layer encoder of the scalable video encoder to generate a second sub-bitstream, wherein portions of the video sequence being encoded in the second layer encoder are predicted using reference portions of the video sequence encoded in the first layer encoder, combining the first sub-bitstream and the second sub-bitstream to generate the scalable bitstream, and signaling in the scalable bitstream an indication of a maximum decoded picture buffer (DPB) size needed for decoding the second sub-bitstream and the first sub-bitstream when the second sub-bitstream is a target sub-bitstream for decoding.

Abstract: A method and apparatus for estimating stereo misalignment using modified affine or perspective model. The method includes dividing a left frame and a right frame into blocks, comparing horizontal and vertical boundary signals in the left frame and the right frame, estimating the horizontal and the vertical motion vector for each block in a reference frame, selecting a reliable motion vectors from a set of motion vectors, dividing the selected block into smaller features, feeding the data to an affine or a perspective transformation model to solve for the model parameters, running the model parameters through a temporal filter, portioning the estimated misalignment parameters between the left frame and right frame, and modifying the left frame and the right frame to save some boundary space.

Abstract: In an embodiment of the invention, a method of fabricating a floating-gate NMOSFET (n-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves as the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: In at least some embodiments, a receiver includes channel estimation logic configured to a process a long training field symbol having a doubled cyclic prefix. The channel estimation logic is configured to vary an amount of the doubled cyclic prefix used for channel estimation. Further, in some embodiments, a wireless communication device includes logic to enable communications based on at least two long training field symbols having a doubled cyclic prefix as part of a synchronization header. Further, in some embodiments, a method includes receiving a long training field symbol having a synchronization header with a doubled cyclic prefix and varying an amount of the doubled cyclic prefix used for channel estimation.

Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.

Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

Abstract: A method for automatic convergence of stereoscopic images is provided that includes receiving a stereoscopic image, generating a disparity map comprising a plurality of blocks for the stereoscopic image, clustering the plurality of blocks into a plurality of clusters based on disparities of the blocks, selecting a cluster of the plurality of clusters with a smallest disparity as a foreground cluster, determining a first shift amount and a first shift direction and a second shift amount and a second shift direction based on the smallest disparity, and shifting a left image in the stereoscopic image in the first shift direction by the first shift amount and a right image in the stereoscopic image in the second shift direction by the second shift amount, wherein the smallest disparity is reduced.

Abstract: A flip chip mounting board includes a substrate having a top surface and a plurality of generally parallel, longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. A first strip of laterally extending solder resist material overlies the first longitudinal end portions of the bond fingers. The first strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps with a longitudinally extending tooth portion being aligned with every other one of the bond fingers. Adjacent bond fingers have first end portions covered by different longitudinal lengths of solder resist material.

Abstract: For coding at least one region of interest within an image of multiple views, disparities are identified between the multiple views. In response to the disparities, the at least one region of interest is identified. The at least one region of interest is encoded at lower quantization relative to a remainder of the image. The remainder of the image is encoded at higher quantization relative to the at least one region of interest.

Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Abstract: A method of generating normalized bit log-likelihood ratio (LLR) values. A signal is received in a frequency band after transmission over a media, wherein the signal includes at least one complex data symbol having a plurality of information bits, and the complex data symbol is transmitted on at least one frequency channel. Initial LLR values are calculated for each of the plurality of information bits based on bit-to-symbol mapping of modulation and noise variance information from the complex data symbol. An average signal to noise ratio (SNR) of the frequency channel is calculated. Each initial LLR value is normalized by dividing by the average SNR to generate a plurality of normalized LLR values. The normalized LLR values may be quantized to provide a finite-bit representation.

Abstract: A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.

Abstract: Continuous time sigma delta (??) analog-to-digital conversion (ADC) circuitry and method in which current mode ?? ADC circuitry is driven directly by current mode mixing circuitry, thereby avoiding a need for a current-to-voltage driver between the input signal mixing circuitry and ?? ADC circuitry.

Abstract: UE-initiated accesses within a cellular network are optimized to account for Doppler shift. A user equipment (UE) receives information that designates a particular access slot as high-speed and designates another access slot as low-speed within a given cell. The UE determines its relative speed to a serving base station (NodeB) within the cell. The UE selects either a baseline structure or an alternate structure if the relative speed is less than a threshold value or only an alternate structure if the relative speed exceeds the threshold value. The UE transmits a signal to the NodeB using the selected structure, such that the baseline structure is transmitted only in the designated low-speed access slot and that the alternate structure is transmitted only in the designated high-speed request slot.

Abstract: In this invention wireless communication of data between a user equipment and a base station including bandwidth aggregation of a plurality of component carriers, includes a first unit transmitting on a first component carrier a grant control signal the other unit specifying a second component carrier different to transmit the typically via a carrier indication field of 3 bits. The carrier indication field can be a one-to-one mapping to each possible second component carrier of a component carrier offset from an anchor carrier, which could be the first component carrier.

Abstract: An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.