Abstract: A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses and stores the prefetch addresses in slots of the prefetch unit buffer. Each slot includes a buffer for storing a prefetch address, two data buffers for storing data that is prefetched using the prefetch address of the slot, and a data buffer selector for alternating the functionality of the two data buffers. A first buffer is used to hold data that is returned in response to a received memory request, and a second buffer is used to hold data from a subsequent prefetch operation having a subsequent prefetch address, such that the data in the first buffer is not overwritten even when the data in the first buffer is still in the process of being read out.

Abstract: An audio downlink path is provided including a Dynamic Range Boost (DRB), a modified Digital-to-Analog Converter (DAC), and a modified audio driver gain control to produce a very high Dynamic Range (DR) while maintaining a limited scale and complexity of the components within the audio downlink path.

Abstract: A volume level and crossfade controller with programmable fades and audio stream priority controls saturation for a multiple audio stream mixer. Start of fade and end of fade events trigger updates of relative volume level targets and volume ramps.

Abstract: An apparatus is provided. Latches are coupled in series with one another in a ring configuration. Each latch includes a tri-state inverter, a first resistor-capacitor (RC) network, and a second RC network. The tri-state inverter has a first clock terminal and a second clock terminal. The first RC network is coupled to the first clock terminal. The second RC network is coupled to the second clock terminal. A biasing network is also provided. The biasing network has a first bias voltage generator that is coupled to the first RC network for each latch and a second bias voltage generator that is coupled to the second RC network for each latch.

Abstract: A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.

Abstract: Surface plasmon resonance (SPR) sensor biointerface with a rigid thiol linker layer and/or interaction layer ligand loading with reversible collapse and/or iron oxide nanoparticle sensor response amplification.

Abstract: Automatic gain control in a receiver. A method for controlling operating range of an analog-to-digital converter (ADC) by an automatic gain control circuit includes estimating a peak-to-average ratio corresponding to an analog signal from digital samples of the analog signal. The method includes determining a peak value corresponding to the analog signal based on the peak-to-average ratio. Further, the method includes maintaining magnitude of the analog signal at an input of the ADC and gain of the receiver based on the peak value.

Abstract: Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).

Abstract: In an embodiment, a delay circuit includes a ring oscillator circuit and a counter circuit. The ring oscillator circuit includes a delay chain having delay elements and configured to generate one of more clock cycles of an oscillator clock signal in response to a clock cycle of a clock signal. The counter circuit includes two counters that are configured to store a count state corresponding to a number of clock cycles of the oscillator clock signal during a single clock cycle of the clock signal. A first buffer is configured to store the number of clock cycles of the oscillator clock signal. The delay circuit includes a buffer to store a bit pattern corresponding to a number of delay elements traversed in a partial clock cycle of the oscillator clock signal in response to the clock cycle of the clock signal based on outputs of the plurality of delay elements.

Abstract: An apparatus is provided. A differential pair of transistors is configured to receive a first differential signal having a first frequency, and a transformer, having a primary side and a secondary side is provided. The primary side of the transformer is coupled to the differential pair of transistors, and the secondary side of the transformer is configured to output a second differential signal having a second frequency, where the second frequency is greater than the first frequency. A first transistor is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, where the first transistor is of a first conduction type. A second transistor is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, where the second transistor is of a second conduction type.

Abstract: A flip chip mounting board includes a substrate having a top surface and a plurality of generally parallel, longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. A first strip of laterally extending solder resist material overlies the first longitudinal end portions of the bond fingers. The first strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps with a longitudinally extending tooth portion being aligned with every other one of the bond fingers. Adjacent bond fingers have first end portions covered by different longitudinal lengths of solder resist material.

Abstract: A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract: A method for computation of a depth map for corresponding left and right two dimensional (2D) images of a stereo image is provided that includes determining a disparity range based on a disparity of at least one object in a scene of the left and right 2D images, performing color matching of the left and right 2D images, performing contrast and brightness matching of the left and right 2D images, and computing a disparity image for the left and right 2D images after the color matching and the contrast and brightness matching are performed, wherein the disparity range is used for correspondence matching of the left and right 2D images.

Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.

Abstract: The present invention relates to an outer dome configured to provide protection and optical correction to a system of projection optics and the output thereof. More particularly, an optical projection system having an optical offset of greater than 100% is comprised within a projector housing having an outer dome comprised of an optically active material mounted onto an opening approximately coinciding with the optical projection system's exit pupil. The outer dome is configured to be decenterized from the exit pupil (e.g., the center of the dome is offset from the exit pupil in one or more of an x, y, and z direction) such that it provides optical correction to a projected image. Therefore, an outer dome is configured to provide protection to optical elements provided therein and improvement of projected image quality (e.g., reduced image distortion, reduced aberration).

Abstract: Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current.

Abstract: A method and system of accessing display window memory. At least some of the illustrative embodiments are methods comprising abstracting display window memory by way of a first software object, accessing the display window memory by routines of a graphics library executed on a first processor (the accessing by way of the first software object), and displaying a window on a display screen, contents of the window selected at least in part by the routines of the graphics library.

Abstract: A method for encoding a video sequence in a scalable video encoder is provided that includes selecting a first search window configuration for coding a current picture of the video sequence in an enhancement layer encoder of the scalable video encoder based on motion vectors generated by a reference layer encoder when encoding the current picture, and coding the current picture in the enhancement layer encoder using the first search window configuration.

Abstract: A processor and execution units providing intra-processor resource control. A processor includes a processor core and a peripheral. The processor core includes a first execution unit, and a second execution unit coupled to the first execution unit. The peripheral is coupled to the second execution unit. The second execution unit is configured to execute a complex instruction, and includes a status register and resource control logic. The status register includes a resource control field configured to store resource control information. The resource control information specifies whether the second execution unit requests access to the peripheral during execution of an instruction stream comprising a complex instruction. The resource control logic is configured to apply the resource control information to request access to the peripheral during execution of the instruction stream comprising the complex instruction.