Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: Embodiments of the invention provide a method of decoding of hexagonal constellations. The decoding methods exploit the inherent structure of the hexagonal grid to eliminate/minimize the requirements for distance computations. A constellation which has unused constellation points is received. A plurality of lookup tables is used for indicating whether a particular constellation point is used. The lookup tables are indexed using the two integers u and v. An initial estimate ? and v is found. The euclidean distance to the immediate neighbors resulting in the immediate upper and lower integers for ? and v is computed. From the distance to the nearest neighbor, the log-likelihood ratio value is computed.

Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.

Abstract: An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe. A shunt is located within the open space such that it is not in contact with any portion of the leadframe.

Abstract: Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead.

Abstract: A power converter (such as a battery charger) includes a cable configured to deliver a source voltage and current to a load, where the cable is anticipated to drop some voltage as the load current increases. The power converter also includes a regulator having a feedback-adjusting transistor configured to gradually compensate for the dropped cable voltage as the load current increases. The transistor has a gate capacitance and a resistance forming an integrator configured to filter a volt-second product of an output waveshape of the converter to derive an average voltage correlated to the load current as the load current increases. The regulator is configured to increase a gate voltage of the transistor through a threshold region of the transistor and gradually turn the transistor on. The transistor is configured to apply an adjusting resistance coupled to a feedback sensing node of the regulator to increase the source voltage to compensate for the cable voltage drop and improve the load voltage regulation.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.

Abstract: An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Abstract: Various systems and methods for LCD backlight control are disclosed herein. For example, some embodiments of the present invention provide an LCD backlight circuit with an analog inverter circuit that provides a drive voltage to a lamp. A current traversing the lamp is sensed and provided to a digital control circuit. Based on the sensed current, the digital control circuit generates a control signal that is fed back to the analog inverter circuit. In some cases, the digital control circuit is used to cause a gradual increase in voltage applied to the lamp to achieve ignition of the lamp. In other cases, the digital control is used to provide a pre-distorted sine wave that attenuates one or more harmonics introduced into the system by the non-linearities of the lamp.

Abstract: An apparatus is provided. A differential pair of transistors is configured to receive a first differential signal having a first frequency, and a transformer, having a primary side and a secondary side is provided. The primary side of the transformer is coupled to the differential pair of transistors, and the secondary side of the transformer is configured to output a second differential signal having a second frequency, where the second frequency is greater than the first frequency. A first transistor is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, where the first transistor is of a first conduction type. A second transistor is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, where the second transistor is of a second conduction type.

Abstract: A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions.

Abstract: Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Abstract: A power supply converter (100) comprising a first FET (210) connected to ground (230), the first FET coupled to a second FET (220) tied to an input terminal (240), both FETs conductively attached side-by-side to a first surface of a metal carrier (120) and operating as a converter generating heat; and a packaged load inductor (110) tied to the carrier and an output terminal (241), the inductor package wrapped by a metal sleeve (113) in touch with the opposite surface of the metal carrier, the sleeve operable to spread and radiate the heat generated by the converter.

Abstract: A wireless device comprises a first wireless transceiver, a second wireless transceiver, and control logic. The control logic is coupled to the first wireless transceiver and the second wireless transceiver. The control logic is configured to determine whether to transmit protection frames (e.g., clear-to-send 2 self frames) based upon sequence numbers in frames received from another device.

Abstract: This invention sets conditions for user equipment responses to channel state indicator request in channel state information that may conflict.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Abstract: Apparatus, systems, and methods disclosed herein operate to calibrate path loss parameters corresponding to a communication channel between wireless stations, including a path loss exponent. A time-of-flight (TOF) associated with packet transmissions traversing a path between a first wireless station and a second wireless station is measured. A path length D1 corresponding to the path is calculated from the TOF measurements. One or more received signal strength (RSS) measurements corresponding to the packet transmissions are then made at the first wireless station. The path loss exponent associated with the path is calculated from D1 and the RSS measurements. Some embodiments may also measure RSS values associated with transmissions from a third wireless station. The latter measurements may be used in conjunction with the previously-determined path loss exponent to derive an unknown transmission path length between the first and third wireless stations.