Patents Assigned to Texas Instruments
  • Sorting frequency arrays to account for multi-protocol frequencies
    Patent number: 8681762
    Abstract: A system comprises transceiver logic that receives signals on each of an array of frequencies. The transceiver logic is adapted to communicate using a first communication protocol. Processing logic couples to the transceiver logic. The processing logic identifies from among the array of frequencies a subset of shared frequencies that carry data transmitted using a second communication protocol. The processing logic adjusts frequency selection parameters in accordance with the identification. The processing logic uses the adjusted frequency selection parameters to select a target frequency from the array of frequencies to carry data.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Katrin Matthes
  • Backgrind process for integrated circuit wafers
    Patent number: 8679945
    Abstract: An integrated circuit is formed by coating a top surface of a wafer that has been processed through all integrated circuit chip manufacturing steps prior to backgrind with photoresist, applying backgrind tape over a top surface of the photoresist, backgrinding a back surface of the wafer to a specified thickness, removing the backgrind tape from the top surface of the photoresist, and removing the photoresist. The surface of the integrated circuit and any devices that may be bonded to the surface of the integrated circuit are protected by the photoresist layer during removal of the backgrind tape.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory A. Moore, Tyonda Hill
  • Termination of prefetch requests in shared memory controller
    Patent number: 8683133
    Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sajish Sajayan, Alok Anand, Ashish Rai Shrivastava, Joseph R. Zbiciak
  • Structure and method for integrating front end SiCr resistors in HiK metal gate technologies
    Patent number: 8680618
    Abstract: An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Ebenezer Eshun
  • Controlling power chain with same controller in either of two different applications
    Patent number: 8680895
    Abstract: A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Ashley Carpenter, Tetsuo Tateishi
  • Power on reset generation circuits in integrated circuits
    Patent number: 8680901
    Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Aatmesh Shrivastava, Rajesh Yadav
  • Wireless communications system with secondary synchronization code based on values in primary synchronization code
    Patent number: 8681834
    Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Anand G. Dabak, Sundararajan Sriram, Srinath Hosur
  • Programmable mapping of external requestors to privilege classes for access protection
    Patent number: 8683115
    Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Dheera Balasubramanian, Joseph R. M. Zbiciak
  • Device security features supporting a distributed shared memory system
    Patent number: 8683114
    Abstract: A memory management and protection system that incorporates device security features that support a distributed, shared memory system. The concept of secure regions of memory and secure code execution is supported, and a mechanism is provided to extend a chain of trust from a known, fixed secure boot ROM to the actual secure code execution. Furthermore, the system keeps a secure address threshold that is only programmable by a secure supervisor, and will only allow secure access requests that are above this threshold.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph R. M. Zbiciak, Amitabh Menon
  • Semiconductor GMI magnetometer
    Patent number: 8680854
    Abstract: A giant magneto-impedance (GMI) magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the GMI magnetometer. The semiconductor wafer fabrication sequence forms a magnetic conductor, a non-magnetic conductor that is wrapped around the magnetic conductor as a coil, and non-magnetic conductors that touch the opposite ends of the magnetic conductor.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Terry Dyer, Anuraag Mohan, Peter J. Hopper
  • On current in one-time-programmable memory cells
    Patent number: 8679929
    Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Shanjen “Robert” Pan, Allan T. Mitchell, Weidong Tian
  • 3D TAP AND SCAN PORT ARCHITECTURES
    Publication number: 20140082441
    Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Region of Interest (ROI) Request and Inquiry in a Video Chain
    Publication number: 20140079118
    Abstract: A method for video stream processing in a video chain is provided that includes transmitting a video stream in the video chain, receiving, by a first video node in the video chain, a region of interest (ROI) command from a second video node in the video chain, wherein the ROI command includes an ROI type indicator, and performing, by the first video node, the ROI command according to the ROI type indicator.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Goksel Dedeoglu, Madhukar Budagavi
  • GRADIENT AOCV METHODOLOGY ENABLING GRAPH-BASED TIMING CLOSURE WITH AOCV TIMING MODELS
    Publication number: 20140082576
    Abstract: A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Raashid Moin Shaikh, Vishnuraj Arukat Rajan
  • BUFFFERED CONDUITS FOR HIGH THROUGHPUT CHANNEL IMPLEMENTATION, CROSSTALK DE-SENSITIZATION AND LATE TIMING FIXES ON SKEW SENSITIVE BUSES
    Publication number: 20140082248
    Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Raashid Moin Shaikh, Vishnuraj Arukat Rajan
  • ADVANCED SWITCH NODE SELECTION FOR POWER LINE COMMUNICATIONS NETWORK
    Publication number: 20140079142
    Abstract: An algorithm for the promotion of terminal nodes to switch nodes in a PLC network reduces overall network overhead and collisions, while ensuring the appropriate selection of a switch node and minimizing the number of levels in a PLC network. It also ensures that the terminal nodes with appropriate signal-to-noise ratios (SNRs) are promoted. It is desirable to have a network with fewer levels. The disclosed approach favors the nodes that are closer to the DC to promote them as switch nodes. This is achieved by waiting for a smaller number of PNPDUs for a node that is closer to the DC in comparison to a node that is farther away from the DC.
    Type: Application
    Filed: September 15, 2012
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Ramanuja Vedantham, Kumaran Vijayasankar, Xiaolin Lu
  • GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS
    Publication number: 20140082442
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Application
    Filed: November 20, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • STATIC RANDOM ACCESS MEMORY CELL WITH SINGLE-SIDED BUFFER AND ASYMMETRIC CONSTRUCTION
    Publication number: 20140078819
    Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Xiaowei Deng, Wah Kit Loh, Anand Seshardi, Zhonghai Shi
  • System and method for input voltage transient response control
    Patent number: 8675375
    Abstract: The present invention provides a DC/DC converter for use with a DC input signal. The DC/DC converter includes a control signal generator, a primary and a secondary side, a voltage generating portion, a threshold voltage providing portion and a feedback signal generator. The control signal generator can control the primary side and the secondary side. The voltage generating portion can generate a surge voltage based a control signal from the control signal generator. The threshold voltage providing portion can generate a threshold voltage. The feedback signal generator can generate a feedback signal based on the surge voltage and the threshold voltage. The control signal generator can further modify control of one of the primary and secondary sides based on the feedback signal.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Shanguang Xu, Zhong Ye
  • Device, method, and medium for optimizing simultaneous long term evolution (LTE) signals and signals in the industrial, scientific, and medical (ISM) radio band
    Patent number: 8676248
    Abstract: A wireless communication device includes a processing unit with first chip and second chip that operates in parallel with the first chip. The first chip transmits/receives data according to LTE. The second chip transmits/receives data over a WLAN. The processing unit determines access points (AP) through which data can be transmitted/received by the second chip over the WLAN; and identifies an optimal AP, based on factors including a determination, for each AP, of whether transmission/reception of data by the first chip according to the LTE standard, simultaneous to transmission/reception of data over the WLAN by the second chip, would decrease the overall throughput of the first and second chips. When the second chip is previously connected to the WLAN through any AP other than the optimal AP, the second chip is disconnected from the other AP, and it is connected to the WLAN through the optimal AP.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Uri Weinrib, Alon Paycher, Keren Dor