Abstract: A method and apparatus for predicting reference data transfer scheme for motion estimation. The method includes computing, via the processor, hypothetical rectangle region in reference frame containing all the predicting and reference data for doing motion estimation search around the region, if the macroblock is not the first in a row, utilizing overlap with previously fetched reference data, computing overlap with previously fetched reference data, and transferring needed data, invalidating any predictor, wherein the predictor is not part of the fetched data, and regulating the motion estimation and setting the motion vector to an effective value based on the fetched and computed data.

Abstract: An adaptive impedance matching module having an adjustable impedance matching network with an input for receiving an RF power source and an output to be connected to an antenna, and first and second voltage measurement device configured to sense a voltage at respective first and second nodes on the impedance matching network. A network adjuster circuit is provided to switch the impedance matching network between a first state where first and second voltages are sensed on the respective first and second nodes and a second state where third and fourth voltages are sensed on the respective first and second nodes. Processing circuitry is provided which determines the matched load impedance based upon the first, second, third and fourth sensed voltages and including matching adjustment circuitry configured to adjust the matching impedance in the event the matched load impedance differs from a target load impedance by more that a predetermined amount.

Abstract: One aspect of the present invention includes a reference current generator circuit. The circuit includes a bias circuit configured to generate a reference current along a first current path and a second current along a second current path. The reference current and the second current can be proportional. The circuit also includes a first pair of transistors connected in series and configured to conduct the reference current in the first current path. The circuit further includes a second pair of transistors connected in series and configured to conduct the second current in the second current path. The second pair of transistors can be coupled to the first pair of transistors to provide a collective resistance value of the second pair of transistors that is proportional to temperature.

Abstract: An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.

Abstract: An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level.

Abstract: An integrated system comprising both imaging and computing capabilities comprises a light valve and a CPU, as well as other functional members for performing computing and imaging.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: Apparatus, systems, and methods disclosed herein operate to provide wireless communication between personal mobile communication (PMC) devices. An emulated wireless access point (AP) at a first PMC device (PMC1) establishes a first tunneled direct link setup (TDLS) session between a first station module (STA1) incorporated into the PMC1 and a second station module (STA2) incorporated into a second PMC device (PMC2). Following establishment of the TDLS session, the wireless AP is allowed to sleep; and most infrastructure management duties are handled by the STA1 during the session. PMC device battery charge may be conserved as a result. The emulated wireless AP may also establish a second TDLS link to a third station module (STA3) incorporated into a third PMC device (PMC3). The STA1 may then bridge data traffic flow between the STA2 and the STA3. Such bridging operation may enable communication between two PMC devices otherwise unable to decode data received from the other.

Abstract: A ball grid array (BGA) includes a plurality of metal balls adapted for connection between an electrical circuit and a substrate. A first portion of the BGA contains a first group of the metal balls arranged according to a first pitch. A second portion of the BGA contains a second group of metal the balls arranged according to a second pitch that is less than the first pitch, to provide increased metal contact area and correspondingly enhanced thermal transfer capability.

Abstract: A system (1-2) for efficiently transferring harvested vibration energy to a battery (6) includes a piezo harvester (2) generating an AC output voltage (VP(t)) and current (IPZ(t)) and an active rectifier (3) to produce a harvested DC voltage (Vhrv) and current (Ihrv) which charge a capacitance (C0). An enable circuit (17) causes a DC-DC converter (4) to be enabled, thereby discharging the capacitance into the converter, when a comparator (A0,A1) of the rectifier which controls switches (S1-S4) thereof detects a direction reversal of the AC output current (IPZ(t)). Another comparator (13) causes the enable circuit (17) to disable the converter (4) when the DC voltage exceeds a threshold (VREF), thereby causing the capacitance be recharged.

Abstract: An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: A recursive method for computing numerical values for mathematical functions includes providing a recursive Taylor series representation of a mathematical function f(x) of a variable x evaluated around a given operating point a. The recursive Taylor series representation includes a plurality of derivative derived terms that include ratios of derivatives of f(x) evaluated at the operating point a. Coefficient data is determined from ones of the derivative derived terms stored in a tangible memory device evaluated at the operating point a over a predetermined range. An approximation for the mathematical function f(x) is computed using the recursive Taylor series representation evaluated with the coefficient data.

Abstract: An electronic device for optimizing the output power of a solar cell, the electronic device having: a variable resistor coupled in series between the solar cell and a load, a control unit that is configured to control the variable resistor, a sensor for measuring an output voltage and a sensor for measuring the output current of the solar cell, wherein the control unit is configured to vary the resistance of the series resistor over time such that the first order derivative of the output voltage over time has a constant value, to monitor the second order derivative of the output current over time simultaneously, to detect whether the second order derivative of the output current over time exceeds a predetermined threshold value and to identify the corresponding values of the output voltage and current as a maximum power point (MPP) of the solar cell.

Abstract: Analog pulse width modulation (PWM) control circuits and techniques are presented for improving output voltage load transient response in controlling DC to DC conversion systems in which a transient detector circuit restarts a PWM carrier ramp waveform to initiate asynchronous injection of a pulse between the regular periodic PWM pulses in a fixed frequency pulse stream to mitigate the effect of output inductor energy depletion on output voltage.

Abstract: Several circuits and methods for field-based communication are provided. In an embodiment, a field-based communication circuit includes a receiver circuit, a detection circuit and a control circuit. The receiver circuit is configured to receive a field input signal from a field source. The detection circuit includes a voltage detection circuit and a current detection circuit configured to detect a voltage signal and a current signal, respectively associated with the field input signal. The control circuit is configured to trigger a selection of one of the voltage detection circuit and the current detection circuit based on a detection of a signal magnitude of one of the voltage signal and the current signal relative to at least a first predetermined threshold level, wherein the selection of one of the voltage detection circuit and the current detection circuit facilitates a demodulation of one of the voltage signal and the current signal.

Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.

Abstract: A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing a maximum slice rate for the video sequence, computing a maximum number of slices for the picture based on the maximum slice rate, and encoding the picture wherein a number of slices used to encode the picture is enforced to be no more than the maximum number of slices.

Abstract: A video system includes an encoder for generating a compressed bit stream in response to a received video signal. The encoder includes a mode decision processor that is arranged to determine whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode.” The encoder also includes a mode estimation processor that is arranged to estimate the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row. The encoder also includes a pixel block processor that is arranged to process a pixel block in the second row that is to the right of the left pixel block in response to the estimated mode of the left pixel block.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.