Abstract: Oscillator circuits are disclosed herein. An embodiment of an oscillator circuit includes a first bias circuit and a second bias circuit. An oscillator first connection terminal is coupled to a node, wherein the node is coupled to the first bias circuit and the second bias circuit. An oscillator second connection terminal connected to the second bias circuit. An increase in the oscillation amplitude of the oscillator increases the current in the second bias circuit and causes a reduction in the bias current in the first bias circuit.

Abstract: According to one embodiment of the present invention, a method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when active. The alternating includes deactivating an active light source before an output of a light beam from the active light sources falls below a first predetermined threshold. The alternating further includes activating an inactive light source only after an output of the inactive light source reaches a second predetermined threshold. The method further includes receiving each of the light beams at a modulator. The modulator includes an array of micro-mirror devices.

Abstract: Embodiments of the invention provide a 16 bit floating point signal processor will typically give an order of magnitude more performance than a 32 bit floating point signal processor and about twice as much performance as a 16 bit fixed point processor. Capturing wide dynamic range images in 16 bit floating point format entails representing an iris of a imaging device as an exponent of a floating point number and representing the precision of said imaging device as a mantissa of said floating point number.

Abstract: A video processing device includes a video preprocessor and a video processor. The video processor is configured to facilitate inputting preprocessed digital video data ready for further processing by an encoder or a transcoder, compressing the preprocessed digital video data to form compressed digital video data, and outputting the compressed digital video data. The video preprocessor operable to receive digital video raw data, configured to facilitate preprocessing a macroblock of the digital video raw data so as to output the preprocessed digital video data ready for an encoder or transcoder of the video processor when the macroblock does not indicate SKIP, and not preprocessing the macroblock of the digital video raw data when the macroblock is a SKIP macroblock indicating SKIP, but jumping to process the SKIP macroblock by an entropy encoder of the video processor instead.

Abstract: Maintaining a simultaneous communication between a first wireless station and both an access point and a second wireless station includes the first wireless station gaining an instance of medium access by using applicable medium access protocols. Once the first wireless station gains an instance of medium access, it transmits frames to the access point on an infrastructure network and to the second wireless station on the same infrastructure network or an ad hoc network.

Abstract: An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions.

Abstract: A system and method for channel interpolation in a wireless device. In one embodiment a wireless device includes a channel estimator. The channel estimator is configured to generate estimated channel coefficients for a wireless channel over which the wireless device receives a packet. The channel estimator includes an interpolation filter. The interpolation filter is configured to provide interpolated channel coefficients for a plurality of non-pilot sub-carriers. The interpolated channel coefficients are based on pilot sub-carriers of non-preamble symbols.

Abstract: In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse.

Abstract: Embodiments of the invention provide a step detection. An accelerometer measurement in the form of a multi-dimensional acceleration vector is obtained. The magnitude of the accelerometer measurement is filtered using a low pass filter. A threshold for a down-crossing is provided as is a threshold for an up-crossing. A step detection is triggered if the magnitude of the accelerometer measurement is greater than or equal to the threshold for an up-crossing.

Abstract: An analog-to-digital converter (ADC) comprises a plurality of time-interleaved integrating ADCs having feedback from an integrated output signal. In variations, the time-interleaved integrating ADCs have feedback compensation from at least one measure of quantization error. The time-interleaved integrating ADCs may also share a single comparator and may also share a single current source.

Abstract: A method is provided. A first CMOS switch is deactivated while activating a second CMOS switch to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage. After a first interval, the second CMOS switch is deactivated while activating a third CMOS switch to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage. After a second interval, the third CMOS switch is deactivated while activating a fourth CMOS switch to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage After a third interval, the fourth CMOS switch is deactivated while activating the first CMOS switch to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage.

Abstract: A method for calibrating a reflection compensator is provided. A delay is initially set to a predetermined minimum, and an input pulse is transmitted across a transmission line. A compensation current is then applied after the delay. The reflection from the transmission line is digitized to generate a measurement, and a determination is made as to whether the compensation current substantially compensates for the reflection. If the compensation current does not substantially compensate for the reflection, then the delay is adjusted, and the process is repeated until the compensation current substantially compensates for the reflection.

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract: A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.

Abstract: A system and method for establishing a mutual entity authentication and a shared secret between two devices using displayed values on each device. Unique first private keys and first public keys are assigned to both devices. The public keys are exchanged between the two devices. Both devices compute a shared secret from their own private keys and the received public keys. Both devices compute, exchange, and verify their key authentication codes of the shared secret. If verification is successful, both devices use the shared secret to generate a displayed value. One or more users compare the displayed values and provide an indication to the devices verifying whether the displays match. If the displays match, then the devices compute a shared master key, which is used either directly or via a later-generated session key for securing message communications between the two devices.

Abstract: An improved method for fabricating a semiconductor device provides a mold having a top portion and a bottom portion. The top portion includes recesses suitable for a cavity and a plurality of protrusions shaped as truncated cones. A thin sheet of compliant inert polymer is placed over the surface of the top portion. A molding compound is introduced into the cavity to form a encapsulation body covering a semiconductor chip and linear arrays of contact pads adjacent to the chip. Each conical protrusion matches a contact pad location. The thin sheet of compliant inert polymer is peeled off the top portion. The mold is opened and the encapsulated semiconductor chip is removed.

Abstract: Embodiments of the systems and methods of direct cell attachment for battery cells disclosed herein operate without the protection FETs and the protection IC, thereby enabling the direct attachment of battery cells to the system without compromising safety. A charger IC comprises a switching regulator whose output is used to charge the battery through a pass device. In example embodiments of the disclosed systems and methods of direct cell attachment, a combination of switching FETs and the pass device are used as a protection device instead of the charge and discharge FETs. During normal operation, the pass device may be used to charge the battery using the traditional battery charging profile. Under fault condition, the switching FETs and pass device may be driven appropriately to protect the system.

Abstract: Transmitting a ACK/NACK response in a wireless cellular network by mapping the data value into a cyclic shifted version of a reference signal. A subframe is formed with a plurality of symbols with certain symbols designated as reference signal (RS) symbols. The receiver and transmitter both know when an ACK/NACK response is expected. If an ACK/NACK response is not expected, then an RS is inserted in the duration of symbols designated as RS symbols. If an ACK/NACK response is expected, then the ACK/NACK response is embedded in one or more of the symbols designated as RS symbols. The subframe is transmitted to a receiver, and the receiver can determine the ACK/NACK value in the RS symbol, if present, and also use the RS symbol for coherent demodulation of a CQI (channel quality indicator) or data.

Abstract: A wireless communication device includes a processing unit with first chip and second chip that operates in parallel with the first chip. The first chip transmits/receives data according to LTE. The second chip transmits/receives data over a WLAN. The processing unit determines access points (AP) through which data can be transmitted/received by the second chip over the WLAN; and identifies an optimal AP, based on factors including a determination, for each AP, of whether transmission/reception of data by the first chip according to the LTE standard, simultaneous to transmission/reception of data over the WLAN by the second chip, would decrease the overall throughput of the first and second chips. When the second chip is previously connected to the WLAN through any AP other than the optimal AP, the second chip is disconnected from the other AP, and it is connected to the WLAN through the optimal AP.

Abstract: Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A device comprises at least two dissimilar network technology subsystems, at least one subsystem of which is lower priority than at least another of the dissimilar subsystems. In some embodiments, a device is able to transmit a silencing frame during a transmission window within a lower priority technology network interval. In other embodiments, a device calculates a transmission window, the transmission window to occur within a lower priority technology network interval, and transmits a silencing frame during the transmission window.