Abstract: A thin-oxide current clamp includes a clamp transistor in current-conducting relation between a voltage-sensitive circuit and a common return of a power supply, the clamp transistor responsive to a sense output signal to provide a low-resistance current flow path from the voltage-sensitive circuit to the common return and thereby clamp a voltage in the voltage-sensitive circuit. The thin-oxide current clamp also includes a current source and a reference current mirror, the reference current mirror providing a reference current. Further, the thin-oxide current clamp includes a sense current mirror providing a sense current. Further, the thin-oxide current clamp also includes an output transistor that receives the sense current and provides a current flow to a gate of the clamp transistors if the sense current exceeds the reference current.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: A system and method for classifying a channel with regard to delay spread in a wireless network applying orthogonal frequency division multiplexing. In one embodiment, a wireless receiver includes a channel classifier. The channel classifier is configured to compute a channel estimate corresponding to a channel traversed by a packet received by the wireless receiver. The channel classifier is also configured to partition the channel estimate into a plurality of windows. Each window corresponds to a range of time of the channel estimate. The channel classifier is further configured to assign a delay spread classification to the channel based on a distribution of energy across the windows.

Abstract: A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result.

Abstract: An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n?1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n?1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n?1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.

Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.

Abstract: Embodiments of the invention provide methods for user equipments to implicitly determine the location of the transmission of uplink control signaling information, that is in response to downlink data packet transmissions, using information that is already available through the downlink control signaling for the respective downlink scheduling assignments. No additional explicit downlink control signaling is required for the transmission of the above uplink control signaling from each user equipment.

Abstract: An integrated circuit includes a high voltage n-channel MOS power transistor integrated with a high voltage n-channel MOS blocking transistor. The power transistor and the blocking transistor have electrically coupled drain contact regions. In one embodiment, a drain area of the power transistor is separate from a drain area of the blocking transistor. In another embodiment, the drain area of the power transistor is contiguous with the drain area of the blocking transistor. The power transistor and the blocking transistor have drain extensions with drift areas. The power transistor drift area is laterally adjacent to both sides of the blocking transistor drift area. The drift areas are aligned so that breakdown does not occur between the power transistor and the blocking transistor. The body of the blocking transistor is isolated from the substrate.

Abstract: Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device.

Abstract: An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: A packing insert for disc-shaped objects comprising a ring and a deformable contacting portion supported by the ring and extending from a circumference of the ring. The contacting portion can comprise one or more solid portions extending from the circumference. The solid portions can define a plurality of radially arranged members separated by a plurality of void regions, where the solid portions extending radially from a circumference of the ring.

Abstract: Quantization for oversampled signals with an error minimization searches based upon clusters of possible sampling vectors where the clusters have minimal correlation and thereby decrease reconstruction error as a function of oversampling (redundancy) ratio.

Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad.

Abstract: An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

Abstract: Methods for decoding data are disclosed herein. The data is coded such that a transition from a first state to a second state represents a logic one and a transition from the second state to the first state represents a logic zero. An embodiment includes determining a pulse width for a first pulse and measuring the width of a second pulse, wherein the second pulse occurs directly after the first pulse. The method continues with comparing the second pulse width to at least one first predetermined period and assigning a value to the second pulse width when the second pulse width is within at least one of the first predetermined periods. The method also includes assigning a value to the second pulse width based on the value assigned to the first pulse width when the second pulse width is not within at least one of the first predetermined periods.

Abstract: A plastic package (100) in which a semiconductor chip (101) is adhesively (102) attached to a metal stripe (110a) having an agglomerate structure, and electrically connected to bondable and solderable metal stripes (120) having particulate structures; metal stripes (120) are touching metal stripes (110b) of agglomerate structure to form vertical stacks (150); coats of solder (140) are welded to the agglomerate metal stripes (100a and 110b).

Abstract: A network includes an access point using a first protocol and a station using both the first protocol and a second protocol. The station uses the first protocol before a first threshold and a second protocol after the first threshold. A first duration between the second threshold and the first threshold is at least of sufficient length for the station to receive one data packet from the access point and send an acknowledgment. The station transmits to the access point a current clear-to-send packet at a current time during a current exchange based on success or failure of a previous exchange during which a previous clear-to-send packet was transmitted to the access point at a previous time.