Abstract: A method for capturing video frames from a plurality of video channels is provided. A list of a least two descriptors is formed for each of the plurality of video channels in a memory accessible to a direct memory access (DMA) engine, wherein each of the two or more descriptors for each channel is programmed to define a storage location for a sequential frame of video data for the channel. A sequence of video frames is received from the plurality of video channels, wherein for each channel, video frames are received at a frame rate for that channel. A DMA engine uses descriptors from the list to store video frames as they are received. The list is updated periodically to replace used descriptors.

Abstract: An apparatus comprises a root mean square (‘RMS’) value generator; an integrator coupled to the RMS value generator; a sample and hold switch coupled to an output of the integrator; a capacitor coupled between the sample and hold switch and a ground; an input of the analog to digital convertor (‘ADC’) coupled to the capacitor; an adder coupled to an output of the ADC; a register, wherein an output of the register is coupled to an input of the adder; and wherein an output of the adder is coupled to an input of the register; and a logic coupled to the register for comparing an output of the register to an RMS threshold value for determining whether a touch-down has occurred.

Abstract: Disclosed herein is a system and method for executing a series of instructions on a circuit. The system comprises an encoder that receives event data corresponding to the executed instructions. The encoder groups the event data into one or more groups and outputs the highest priority event for each such group.

Abstract: An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound.

Abstract: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT2 current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT2 and ICTAT2, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier.

Abstract: A method for generating a desired haptics effect is provided. A haptics effect instruction is generated by a host processor responsive to a touch screen, where the haptics effect instruction corresponds to the desired haptics effect. This haptics effect instruction is received by a haptics driver, and a haptic profile from the haptics effect instruction is generated from the haptics effect instruction. The haptic profile includes at least one of a profile word, a move word, wait/halt word, and a branch word, and a sine wave is generated from the from the haptic profile that corresponds to the desired haptics effect.

Abstract: The invention provides a solid-state image pickup device and method for realizing a higher sensitivity and a higher S/N ratio especially in the low-luminance region while maintaining a wide dynamic range.

Abstract: The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

Abstract: Embodiments of the invention provide time-domain link adaptation in power line communications. In one embodiment, the cyclic prefix length and position is adjusted with an OFDM symbol to overlap a periodic impulse noise pulse, thereby allowing the data carried in the symbol to be detected at a receiver. The cyclic prefix may be adjusted to provide a pattern that yields an integer number of OFDM symbols in one zero crossing period. The data rate used for the symbols overlapping the zero-crossing period may be zero or very low. A high data rate may be used for symbols outside the zero-crossing period because those symbols will not be affected by the periodic impulse noise.

Abstract: Today, 100BaseT is commonly used in industrial Ethernet application. As a result of being in such an environment, Ethernet cables are subject to abuse, which can result in costly failures and repairs. Here, a system is provided that enables use of remaining and largely undamaged twisted-pairs within Ethernet cables to maintain 100BaseT connections without costly repairs and failures.

Abstract: A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Abstract: A wireless location assist device (WLAD) comprises control logic and a wireless radio coupled to the control logic. The control logic causes the radio to perform at least one of wireless local area network (WLAN) beacon transmission and WLAN probe request receipt and response. The control logic never permits the WLAD to associate with a wireless station.

Abstract: A method is provided. A first voltage is applied to a first set of column electrodes within a touch panel during a first interval, and a second voltage is applied to a second set of column electrodes within the touch panel during the first interval. The first and second sets of electrodes are adjacent to one another, and the second voltage has the opposite polarity of the first voltage. During the first interval, a first measurement signal is received from a set of row electrodes in the touch panel, and the first measurement signal is integrated to generate a first integrated signal. The first voltage is applied to the second set of column electrodes within the touch panel during a second interval, and the second voltage is applied to the first set of column electrodes within the touch panel during the second interval.

Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.

Abstract: A system for controlling a motor (3) includes a driver circuit (5) for generating a drive voltage (v) to generate a phase current (i) in the motor. Phase current sensing circuitry (10,21) digitizes the phase current. A first circuit (23) provides a reconstructed digital representation of a BEMF signal (vbemf) of the motor to generate an error-corrected synchronization signal (SYNC) in response to the phase current and a detected error in the motor speed, an amplitude feedback signal (15), and information (iR,iL,?iL,vL) indicative of a resistance (Rm) and an inductance (Lm) of the motor. A motor drive signal (15) having an error-corrected frequency is generated in response to the synchronization signal. A PWM circuit (16) produces a PWM signal (17) having a frequency equal to the error-corrected frequency of the synchronization signal (SYNC) and a duty cycle controlled according to the detected error.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A voltage regulator controls a regulated output voltage (Vout) by feeding it back to a differential input stage (13) receiving a reference voltage (Vref) and applying an output (3) to a control electrode of a follower transistor (M4) that is coupled to an output stage (15) which generates the output voltage (Vout). The output stage operates pull-up (M7B) and pull-down (M5B) transistors in response to a signal (6A) produced by the follower transistor (M4) during normal regulation operation, and provides fast settling of the output voltage by turning on a transient pull-up transistor (M7A) or transient pull-down transistor (M5A) in response to the signal (6A) produced by the follower transistor (M4) during a fast increasing or decreasing transition, respectively, of the load current (IL). A filtering resistor (RFLT) is coupled between the output voltage and a common electrode of the transient pull-up and pull down transistors.

Abstract: A motion conversion system is described. The motion conversion system comprises a first torsional member operative for rotating in a first direction. A second torsional member is offset a distance from the first torsional member, wherein the second torsional member is operative for rotating in a direction opposite from the first direction. And, a lateral member has a lower surface connected to the first and second torsional members. Wherein, translational movement of the lateral member results from rotational movement of the first and second torsional members.

Abstract: A wireless device includes a first wireless transceiver and a second wireless transceiver. The first wireless transceiver is configured to communicate via a first wireless network, and includes a first scheduler configured to schedule communication via the first wireless network. The second wireless transceiver is configured to communicate via a second wireless network. The second wireless transceiver includes a second scheduler. The second scheduler is configured to identify a resource allocated to the second wireless transceiver for a transaction via the second wireless network, to identify a portion of the resource used by the second wireless transceiver for the transaction, and to transfer information defining the portion to the first transceiver.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.