Abstract: Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A device comprises at least two dissimilar network technology subsystems, at least one subsystem of which is lower priority than at least another of the dissimilar subsystems. In some embodiments, a device is able to transmit a silencing frame during a transmission window within a lower priority technology network interval. In other embodiments, a device calculates a transmission window, the transmission window to occur within a lower priority technology network interval, and transmits a silencing frame during the transmission window.

Abstract: A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage.

Abstract: Circuits and methods for controlling Pulse Width Modulation (PWM) input of a driver circuit during transition of states are provided. The driver circuit is operative in one of a high state, a low state and a tri-state based on the PWM input. The method includes receiving a tri-state command for transition from the high state to the tri-state. A PWM output signal is enabled to transition from a high logic value to a low logic value for driving the driver circuit from the high state to the low state upon receipt of the tri-state command. The PWM output signal is enabled to transition from the low logic value to a tri-state logic value for driving the driver circuit from the low state to the tri-state upon elapse of a threshold time delay. The PWM input to the driver circuit is based on the PWM output signal.

Abstract: Dynamic adjustment of noise filter strengths for use with dynamic range enhancement of images is performed to produce better quality images by adapting dynamically to the image noise profile. Global and local brightness and contrast enhancement (GLBCE) is performed on a digital image to form an enhanced image. The GLBCE applies local gain values to the digital image based on local intensity values. A GLBCE gain versus intensity curve is determined for the enhanced image. A set of noise filter thresholds is adjusted in response to the GLBCE gain versus intensity curve to form a set of dynamically adjusted noise filter thresholds. The enhanced image is noise filtered using the set of dynamically adjusted noise filter thresholds to form a noise filtered enhanced image.

Abstract: An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection electrodes that are spaced apart and electrically isolated from one another and an associated set of interleavers. Each interleaver is located between adjacent detection electrodes from its associated the set of detection electrodes, and each set of interleavers also includes a pair of complementary interleaving electrodes coupled to those that are electrically coupled to the adjacent detection electrodes from its associated set of detection electrodes. The detection electrodes and interleaving electrodes are also substantially transparent to visible spectrum light.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: A network includes an access point using a first protocol and a station using both the first protocol and a second protocol. The station uses the first protocol before a first threshold and a second protocol after the first threshold. A first duration between the second threshold and the first threshold is at least of sufficient length for the station to receive one data packet from the access point and send an acknowledgment. The station transmits to the access point a current clear-to-send packet at a current time during a current exchange based on success or failure of a previous exchange during which a previous clear-to-send packet was transmitted to the access point at a previous time.

Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

Abstract: A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.

Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.

Abstract: A system comprising a first logic adapted to use qualifiers received from a component to determine which of a plurality of storages matches the qualifiers, the first logic generates a first signal indicative of a storage matching the qualifiers. The system also comprises a second logic coupled to the first logic and adapted to use a target address received from the component to determine which of the plurality of storages matches the target address, the second logic generates a second signal indicative of a storage matching the target address. Another logic is adapted to determine whether the storage associated with the first signal matches the storage associated with the second signal. The qualifiers indicate security mode attributes associated with the component.

Abstract: This invention is computer implemented method of encoding video data into a compressed form. Encoding each macroblock in a frame of video data stores Context based Adaptive Binary Arithmetic Coding (CABAC) data in first and second CABAC engine registers. Each macroblock is classified into either a first type having recoverable CABAC engine registers or a second type having non-recoverable CABAC engine registers. The method closes a slice of data if the current macroblock exceeds a slice data size limit. The method restores or re-encodes previous macroblock CABAC engine registers dependent upon the states of the previous macroblock and the macroblock before that.

Abstract: Method and apparatus for enhancing representations of micro-calcifications in a digital mammogram image. The method includes smoothing the digital mammogram image using a fuzzy smoothing technique to yield a fuzzy smoothed image. The method includes subtracting the fuzzy smoothed image from the digital mammogram image to yield a micro-calcifications enhanced image. The method includes scaling gray level values of pixels in the micro-calcifications enhanced image by a predetermined amount to provide a digital mammogram image with enhanced representations of the micro-calcifications. Apparatus for enhancing representations of micro-calcifications includes an image processing unit that uses an image acquisition unit to receive an image and a digital signal processor to process the image to provide a digital mammogram image with enhanced representations of micro-calcifications.

Abstract: System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that produces a light with desired spectral characteristics, a color filter optically coupled to the light source, and an array of light modulators optically coupled to the color filter. The color filter filters light from the light source to produce light of desired wavelengths and the array of light modulators simultaneously displays multiple images onto a display plane. Portions of the array of light modulators are designed so that each portion can independently display an image and the light source provides needed light to display the image.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: In an embodiment of the invention, a frequency divider in a PLL (phase-locked loop) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first DC (direct current) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.

Abstract: A system and method for arbitrating channel access in a wireless device including co-located network transceivers are disclosed herein. A wireless device includes a first wireless transceiver and a second wireless transceiver. The first transceiver is configured for operation with a first wireless network. The second transceiver is configured for operation with a second wireless network. The wireless device further includes logic that determines which of the first and second transceivers is enabled to transmit at a given time. The logic causes the first transceiver to transmit a notification signal indicating a time period during which the second transceiver of the wireless device will perform a first wireless transaction, and during which, based on receiving the notification signal, a different wireless device performs a second wireless transaction via the second wireless network without transmitting a notification signal.

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.