Abstract: A method is provided for accessing a memory device having pages by a memory interface that does not directly support page accesses. A first memory space of the memory interface is configured with a first set of timing parameters and a second memory space of the memory interface is configured with a second set of timing parameters. A page mode access is initiated to a page of the memory device using the first memory space of the memory interface for at least a first data transfer and continued using the second memory space of the memory interface for a plurality of data transfers.

Abstract: An integrated circuit including a ram array with SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.

Abstract: A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.

Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: A first camera captures first images of first views. A second camera captures second images of second views. First visual features are detected and tracked in the first images. Second visual features are detected and tracked in the second images. A pose is estimated of the second camera in response to the second visual features. In response to determining that the second visual features have better sufficiency than the first visual features, content is displayed to have a fixed pose in response to the estimated pose of the second camera.

Abstract: A first camera captures first images of first views. A display device displays the first images on a screen of the display device. A second camera captures second images of second views. Visual features are detected and tracked in the second images. A pose is estimated of the second camera in response to the tracked visual features. On the first images on the screen, content is superimposed to have a fixed pose in response to the estimated pose of the second camera.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: A method of compressing digital image data is provided that includes, for each image data block in a plurality of image data blocks in the digital image data, transforming image data in the image data block to convert the image data to a low-frequency coefficient and a plurality of high-frequency coefficients, computing a predicted low-frequency coefficient for the image data block based on at least one neighboring image data block in the plurality of image data blocks, computing a residual low-frequency coefficient based on the predicted low-frequency coefficient and the low-frequency coefficient, quantizing the plurality of high-frequency coefficients, and entropy coding the residual low-frequency coefficient and the quantized high-frequency coefficients.

Abstract: An apparatus includes a sensorless field-oriented control (FOC) motor controller. The motor controller includes a pulse width modulation (PWM) controller configured to generate PWM signals and to provide the PWM signals to an inverter. The motor controller also includes an angle sampler configured to receive a commanded voltage angle signal and to provide the commanded voltage angle signal as an output signal in response to a triggering event. The triggering event is based on a voltage or a current associated with an input or an output of the inverter. The motor controller further includes a first combiner configured to combine (i) a feed-forward voltage angle signal and (ii) a second signal based on the output signal. The first combiner is configured to generate the commanded voltage angle signal. In addition, the motor controller includes a second combiner configured to combine a feed-forward voltage amplitude signal and the second signal.

Abstract: The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: Oscillator circuits are disclosed herein. An embodiment of an oscillator circuit includes a first bias circuit and a second bias circuit. An oscillator first connection terminal is coupled to a node, wherein the node is coupled to the first bias circuit and the second bias circuit. An oscillator second connection terminal connected to the second bias circuit. An increase in the oscillation amplitude of the oscillator increases the current in the second bias circuit and causes a reduction in the bias current in the first bias circuit.

Abstract: A camera points in a first direction for capturing images of views. Visual features are detected and tracked in the images. A pose is estimated of the camera in response to the tracked visual features. A projector points in a second direction for projecting content to have a fixed pose in response to the estimated pose of the camera.

Abstract: A method for all-in-focus image reconstruction and depth map generation in an imaging device is provided that includes capturing a multi-focus image by the imaging device, partitioning the multi-focus image into a plurality of blocks, determining, for each block of the plurality of blocks, a best inverse multi-focus point spread function (PSF) for reconstructing original image intensity values in the block, wherein the best inverse multi-focus PSF is selected from a plurality of predetermined inverse multi-focus PSFs stored in a memory of the imaging device, and applying to each block of the plurality of blocks the best inverse multi-focus PSF determined for the block to reconstruct the all-in-focus image.

Abstract: A semiconductor-centered MEMS device (100) integrates the movable microelectromechanical parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.

Abstract: An automated system, and method of operating the same, for assisting the layout of components and the routing of conductors in a layout of an integrated circuit. An asymmetric zoom command is provided, by way of which the user can magnify the current view of a portion of the layout in one dimension while maintaining the original magnification in the orthogonal dimension. The commands can be conveyed by keystrokes, or by a command in combination with a drawn rectangle indicating the extent of the asymmetric zoom magnification. Both asymmetric zoom-in and asymmetric zoom-out are supported.

Abstract: A device for communicating digital data over power lines includes a power line interface for transmitting data over at least one band of frequencies. An orthogonal frequency division multiplexing (OFDM) modulation unit generates OFDM symbols using a set of tones for the frequency band. A preamble generation unit generates preamble sequences for the frequency band by using the set of tones used by the OFDM modulation unit. The tones used by the preamble generation unit have a constant magnitude, and a set of phases obtained by quantizing to a small alphabet the phase of a set of tones obtained by taking an IFFT of a portion of a preamble used by a non-interoperable powerline access device. The device may transmit on two or more bands using a sampling frequency clock, wherein a lower band clock frequency is equal to or an integer divisor of a higher band clock frequency.

Abstract: A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.