Abstract: The level two memory of this invention supports coherency data transfers with level one cache and DMA data transfers. The width of DMA transfers is 16 bytes. The width of level one instruction cache transfers is 32 bytes. The width of level one data transfers is 64 bytes. The width of level two allocates is 128 bytes. DMA transfers are interspersed with CPU traffic and have similar requirements of efficient throughput and reduced latency. An additional challenge is that these two data streams (CPU and DMA) require access to the level two memory at the same time. This invention is a banking technique for the level two memory to facilitate efficient data transfers.

Abstract: An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.

Abstract: An electronic circuit includes a driver for an LED light, having an isolated DC-DC converter having a first output at a higher voltage referred to a floating ground and a second output at a lower voltage than said first output and referred to a reference voltage. A DC-DC boost converter receives its input power from the second output of the isolated DC-DC converter and having its output coupled to the floating ground, whereby an output voltage to a LED light receives the sum of the voltages of the first output of the isolated DC-DC converter and the output of the DC-DC boost converter.

Abstract: A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an application interface such as USB, IEEE 802.3 (Ethernet) and other protocols. The capabilities available include all or many of the capabilities provided by a dedicated debug interface.

Abstract: Embodiments of the invention include a method for creating probe requests. The method is used when positioning is required. A short probe request is constructed with SSID set to GPS SSID_NAME. Another method continues after a short probe response is received. It is determined if a SSID of the probe response matches the SSID of the short probe request. If it does send an ACK.

Abstract: A metal leadframe strip (500) for semiconductor devices comprising a plurality of sites (510) for assembling semiconductor chips, the sites alternating with zones (520) for connecting the leadframe to molding compound runners; the sites (510) having mechanically rough and optically matte surfaces (511, 512); the zones (520) having at least portions with mechanically flattened and optically shiny metal surfaces (521, 522); and the flattened surface portions transitioning into the rough surface portions by a step.

Abstract: A method for determining intra-prediction modes for prediction units (PUs) of a largest coding unit (LCU) is provided that includes determining an inter-prediction mode for each child PU of a PU, and selecting an intra-prediction mode for the PU based on the intra-prediction modes determined for the child PUs.

Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.

Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.

Abstract: A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: This invention is a method of wireless communication using candidate multi-cell CSI-RS time-frequency patterns in the invention. This invention avoids collision with antenna ports 0, 1, 2 and 3 used for transmitting cell-specific reference signals and port 5 used for transmitting demodulation reference signals. This invention satisfies the nested property requirement. This invention avoids collision with DM-RS signal for extended cyclic prefix transmission as long as DMRS Rank is less than or equal to 2. For ranks greater than 2, this invention produces patterns that may collide with Rel. 10 DM-RS for extended CP. The invention includes alternative patterns obtained by relabeling and/or reshuffling the CSI-RS antenna port numbers while preserving identical time-frequency resources assigned to CSI-RS in the time-frequency grid.

Abstract: A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.

Abstract: A method, apparatus and a system for retrieving data relating to at least one of a student's homework, exam or solution to a problem from at least one calculator via a network, wherein the handheld calculator is utilized by the student. The method includes presenting an invitation from at least one of a computer or a calculator of an instructor on the calculator of the student for requesting the data from the calculator of the student, wherein the invitation identifies a location on a computer or a calculator for transmitting the data, attaching the data to at least a portion of the invitation, wherein the data includes identification identifying at least one of the calculator of the student or the student, and transmitting the data from the calculator to the location identified in the invitation.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: A method and circuit for performing channel equalization in a high speed transmission system comprising a transmitter and receiver. An application specific digital signal processor, ASDSP, performs channel equalization and compensation on digital data received from an analogue-to digital converter of the receiver. The ASDSP is operable to execute an application specific set of op-codes needed for performing channel equalization and compensation. An ASDSP register is coupled between the ASDSP and a system CPU in a feedback loop for performing channel equalization at the receiver. The ASDSP stores equalizer parameters and bit error rate measurements used by the ASDSP for performing channel equalization and compensation. An ASDSP program storage memory, coupled to and accessible by the ASDSP, stores an ASDSP micro-sequence program for controlling the processing steps for channel equalization and dataflow through the ASDSP.

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract: For converting a two-dimensional visual image into a three-dimensional visual image, the two-dimensional visual image is segmented into regions, including a first region having a first depth and a second region having a second depth. The first and second regions are separated by at least one boundary. A depth map is generated that assigns variable depths to pixels of the second region in response to respective distances of the pixels from the boundary, so that the variable depths approach the first depth as the respective distances decrease, and so that the variable depths approach the second depth as the respective distances increase. In response to the depth map, left and right views of the three-dimensional visual image are synthesized.

Abstract: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation.