Patents Assigned to Texas Instruments
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Patent number: 8631483Abstract: A packet filter (2500) for incoming communications packets includes extractor circuitry (2510) operable to extract data from a packet, and packet processor circuitry (2520) operable to concurrently mask (3010) the packet data from the extractor circuitry (2510), perform an arithmetic/logic operation (3020) on the packet to supply a packet drop signal (DROP), and perform a conditional limit operation and a conditional jump operation (3030).Type: GrantFiled: May 31, 2006Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Maneesh Soni, Amritpal S. Mundra, Thomas H. McKinney, Jagdish Doma
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Patent number: 8630043Abstract: For combining light from different light sources that are spatially apart, an optical system comprises a prism assembly that comprises a totally-internally-surface and a dichroic filter. The totally-internally-surface and the dichroic filter are configured for reflecting light of different colors or polarizations, so as to combine light of different polarization or colors into a single beam.Type: GrantFiled: August 9, 2011Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Andrew Gerritt Huibers, Regis Grasser
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Patent number: 8629027Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension.Type: GrantFiled: April 4, 2011Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
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Patent number: 8628197Abstract: Display systems and methods for mobile devices and mobile devices are disclosed. In one embodiment, a display system for a mobile device is provided. The mobile device is handheld and includes a primary display screen. The display system includes an auxiliary screen and a connecting device coupled to the auxiliary screen and attachable to the mobile device. An image from the mobile device is producible on the auxiliary screen. The display system is removable from the mobile device.Type: GrantFiled: January 15, 2013Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Leonardo W. Estevez, William R. Krenik, Steven E. Smith, Yoram Solomon, Jose S. Vasquez, Steven Penn
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Patent number: 8629763Abstract: An RFID transponder is provided which includes an automatic gain control (AGC) stage for amplifying a radio frequency (RF) signal and for providing an amplified RF signal. The AGC stage has a control signal indicating an increase of the amplitude of the RF signal. A demodulator is coupled to receive the amplified RF signal for demodulating the amplified RF signal. The demodulator provides a data signal. A burst detector is coupled to receive the control signal of the AGC stage and adapted to provide a start signal in response to a change of the control signal. A wake pattern detector is coupled to receive the data signal and the start signal. The wake pattern detector is adapted to detect a predefined wake pattern in the data signal after having received the start signal and to issue a wake signal if the predefined wake pattern is detected for switching the RFID transponder from a first operating mode into a second operating mode having higher power consumption than the first operating mode.Type: GrantFiled: December 2, 2009Date of Patent: January 14, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Andreas Hagl, Ernst Muellner
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Patent number: 8629759Abstract: An RFID transponder comprises an antenna for receiving data in a downlink mode and transmitting data in an uplink mode, with a modulation stage for modulating uplink data and a demodulation stage for demodulating downlink data. A class C amplifier is provided, which has a resonant circuit, a plucking device coupled to the resonant circuit, and a controllable pulse width generator coupled to the plucking device. The controllable pulse width generator is adapted to periodically switch the plucking device on and off so as to maintain an oscillation of the resonant circuit. The transponder further comprises a phase locked loop configured to be locked to an oscillating signal received through the antenna and to be switched into a free running mode without being locked to the oscillating signal received through the antenna, thereby being adapted to output an independent internal clock signal for the RFID transponder.Type: GrantFiled: August 28, 2008Date of Patent: January 14, 2014Assignee: Texas Instruments Deutschland GmBHInventor: Ernst Muellner
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Patent number: 8627566Abstract: A ceramic header configured to form a portion of an electronic device package includes a mounting portion configured to provide a mounting surface for an electronic device. In addition, the ceramic header includes one or more conductive input-output connectors operable to provide electrical connections from a first surface of the ceramic header to a second surface of the ceramic header. The ceramic header also includes one or more thermally polished surfaces.Type: GrantFiled: April 1, 2010Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Moody K. Forgey, Mark A. Kressley
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Patent number: 8630374Abstract: A packet detection and coarse symbol timing recovery system for preamble signal modulated with rotated differential M-ary phase shift key (PSK) modulation includes a differential detection unit, to provide a symbol signal responsive to a received signal. A preamble sequence correlator performs a preamble sequence correlation on the symbol signal to produce a correlator signal. A metric calculation unit performs a metric calculation on the correlator signal to produce a metric. A packet detection unit determines that a packet is detected and produces a sample index. A coarse symbol timing unit finds a peak of the calculated metric signal outputs a sample index for the peak as coarse symbol timing information. The sample indexes are used in processing a physical layer convergence procedure (PLCP) header and physical layer service data unit (PSDU) block.Type: GrantFiled: September 14, 2010Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: June Chul Roh, Anuj Batra, Srinath Hosur
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Patent number: 8631293Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.Type: GrantFiled: March 27, 2013Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8630240Abstract: A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations on an uplink channel in a wireless network. A scheme for mapping between logical uplink control channel (PUCCH) resource blocks (RBs) and physical RBs (PRBs) used by PUCCH is described. A logical uplink control resource block index nLRB is derived by the secondary node in response to information from the primary node. The secondary node then maps the logical uplink control resource block index nLRB to a first uplink physical resource block index nPRB,1 of a plurality of uplink physical resource blocks. The secondary node then transmits an uplink control information in a subframe using one of the plurality of uplink physical resource blocks indexed by nPRB,1.Type: GrantFiled: February 18, 2009Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Zukang Shen, Tarik Muharemovic, Jing Jiang
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Patent number: 8631289Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.Type: GrantFiled: July 23, 2013Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8629627Abstract: In a first aspect, an LLC resonant converter is provided for driving a plurality of output circuits from a DC input signal. The LLC resonant converter includes: (a) an inverter circuit for converting the DC input signal to a square-wave signal; (b) an inductor network coupled to the inverter circuit; and (c) a plurality of transformers, each transformer including a primary winding and a secondary winding. The primary windings of the transformers are coupled in series, and the series-coupled primary windings are coupled in parallel with the inductor network. The secondary winding of each transformer is coupled to and provides a current to a corresponding one of the output circuits. The secondary winding currents are substantially equal, and power is processed by a single transformer between the DC input signal and each output circuit. Numerous other aspects are also provided.Type: GrantFiled: June 29, 2010Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventors: Isaac Cohen, Bing Lu
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Patent number: 8629021Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.Type: GrantFiled: November 2, 2007Date of Patent: January 14, 2014Assignee: Texas Instruments IncorporatedInventor: Michael Francis Pas
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Publication number: 20140011333Abstract: A method of fabricating an integrated circuit is disclosed (FIGS. 1-2). The method comprises providing a substrate (200) having an isolation region (202) and etching a trench in the isolation region. A first conductive layer (214) is formed within the trench. A first transistor having a first conductivity type (n-channel) is formed at a face of the substrate. The first transistor has a gate (216) formed of the first conductive layer. A second transistor having a second conductivity type (p-channel) is formed at the face of the substrate. The second transistor has a gate (224) formed of the first conductive layer. The method further comprises replacing the first conductive layer of the first transistor with a first metal gate (132) and replacing the first conductive layer of the second transistor with a second metal gate (134).Type: ApplicationFiled: July 9, 2012Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventors: Benjamin P. McKee, Yongqiang Jiang, Douglas T. Grider
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Publication number: 20140013175Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Publication number: 20140010032Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.Type: ApplicationFiled: May 21, 2013Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventors: Anand Seshadri, Dharin Shah, Parvinder Rana, Wah Kit Loh
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Publication number: 20140010337Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.Type: ApplicationFiled: December 11, 2012Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventors: Robert Bogdan Staszewski, Dirk Leipold
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Publication number: 20140013174Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8627145Abstract: This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit.Type: GrantFiled: December 21, 2010Date of Patent: January 7, 2014Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8624610Abstract: A circuit has a first sense resistor circuit having components including a first-circuit active element to provide a sense resistance to sense a current in a load in series therewith, the sense resistance being established by an input command voltage. A second sense resistor circuit has components replicating the components of the first sense resistor circuit including a replicated active element, a resistance of the replicated active element also being established by the input command voltage. A precision resistor is coupled to the replicated active element to provide a load thereto. When the input command voltage establishes a voltage across the replicated active element, a voltage is established across the first-circuit active element in proportion thereto to command a desired current in the load.Type: GrantFiled: February 23, 2011Date of Patent: January 7, 2014Assignee: Texas Instruments IncorporatedInventor: Robert Alan Neidorff