Patents Assigned to Texas Instruments
  • Patent number: 8664706
    Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Shanjen “Robert” Pan, Allan T. Mitchell, Weidong Tian
  • Patent number: 8664968
    Abstract: An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 4, 2014
  • Patent number: 8666346
    Abstract: An FM receiver is unaware of the modulation level (frequency deviation) of the signal and has to make an estimate of it, or some reasonable time-average of it, and accordingly set the input filter's bandwidth. We calculate modulation by measuring the autocorrelation of the recovered audio signal instead of its peaks, and then applying a peakhold detector. Since FM noise can be modeled to be somewhat uncorrelated, we can expect to get an accurate estimate of signal power while rejecting noise power substantially if we measure a one-sample delayed autocorrelation estimate. Since the above measurement is alike a power measurement, we compute its square root, gain adjust it to obtain a cleaner peak measurement, and then track these clean peaks using a leaky integrator. This gives an estimate of modulation that subdues the effect of the noise.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sira Parasurama Rao, John Elliott Whitecar
  • Patent number: 8666735
    Abstract: An IC processor circuit has an interface for a microphone and a packet switched network. A memory holds bits for converting audible speech from the microphone into digital data in each of successive frames. For each frame the converting includes forming LPC data, LTP lag data, parity check data, adaptive and fixed codebook gain data, and fixed codebook pulse data. The digital data representing the audible speech for the frames is placed into sequential packets, with each packet having a primary stage and a secondary stage. The placing includes arranging data from a first frame of speech in the primary stage of a first packet and arranging data from the first frame of speech in the secondary stage of a second packet, which follows the first packet. The data in the secondary stage includes only LPC data, LTP lag data, parity check data, and adaptive and fixed codebook gain data.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Krishnasamy Anandakumar, Vishu Viswanathan, Alan V. McCree
  • Patent number: 8667351
    Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8664080
    Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi, Lily Springer
  • Patent number: 8667355
    Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8665376
    Abstract: Several systems and methods for filtering noise from a picture in a picture sequence associated with video data are disclosed. In an embodiment, the method includes accessing a plurality of pixel blocks associated with the picture and filtering noise from at least one pixel block from among the plurality of pixel blocks. The filtering of noise from a pixel block from among the at least one pixel block includes identifying pixel blocks corresponding to the pixel block in one or more reference pictures associated with the picture sequence. Each identified pixel block is associated with a cost value. One or more pixel blocks are selected from among the identified pixel blocks based on associated cost values. Weights are assigned to the selected one or more pixel blocks and set of filtered pixels for the pixel block is generated based on the weights.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Manu Mathew, Shyam Jagannathan, Soyeb Noomohammed Nagori, Hrushikesh Tukaram Garud
  • Patent number: 8665788
    Abstract: A preamble sequence according to the disclosed systems and methods of setting a preamble sequence for multilevel frequency modulations is comprised of four sections: an initiation sequence, based on a repeatable unique word; a start of frame delimiter, which consists of the negation of the unique word; a continuous wave signal with a certain duration and frequency added after the start of frame delimiter; and an additional sequence for further training of the receiver, also based on repetitions of the unique word and/or its negations.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Tomas Motos, Robin Hoel
  • Patent number: 8662675
    Abstract: A projection lens for projecting images with high degrees of image offset while limiting the physical offset of the projection lens elements. The projection lens arrangement limits the displacement of the optical elements relative to the optical axis of the display panel and enables a very thin, efficient projector.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick Rene Destain
  • Patent number: 8663879
    Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Yong Seok Choi, Thomas J. Aton
  • Patent number: 8665125
    Abstract: The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 4, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Michael Reinhold, Martin Allinger, Frank Ohnhaeuser
  • Publication number: 20140055413
    Abstract: A touch screen system includes a capacitive touch screen (1) including a plurality of row conductors (7-1, 2 . . . n) and a column conductor (5-1). A plurality of cotemporaneous orthogonal excitation signals (S1(t), S2 (t) . . . Sn(t)) are simultaneously driven onto the row conductors, respectively. The capacitively coupled signals on the column conductor may be influenced by a touch (10) on the capacitive touch screen. Receiver circuitry (50) includes a sense amplifier (21-1) coupled to generate an amplifier output signal (r1(t)) in response to signals capacitively coupled onto the column conductor. WHT-based circuitry (35) determines amounts of signal contribution capacitively coupled by each of the excitation signals, respectively, to the amplifier output signal.
    Type: Application
    Filed: November 5, 2013
    Publication date: February 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: William R. Krenik, Anand Dabak
  • Patent number: 8659165
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 8659112
    Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 ? of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Amitabh Jain
  • Patent number: 8660081
    Abstract: Embodiments of the invention provide methods for optimizing the spectral efficiency of control channel transmissions carrying scheduling assignments from a serving Node B to user equipments. This is accomplished by adjusting the control channel size between successive transmission time intervals according to the number of user equipments having scheduling assignments and possibly according to the modulation and coding scheme used for the transmission of each scheduling assignments.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Aris Papasakellariou
  • Patent number: 8658489
    Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 8658474
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 8661303
    Abstract: An operating system independent JTAG debugging system implemented to run in a web browser. The software executing in the browser identifies the JTAG enabled components in the target system that is to be tested and automatically downloads the latest versions of the appropriate software and drivers from a test server database, together with any applicable patches and software updates.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Yee Shun Lau, Vikas Varshney
  • Patent number: 8661374
    Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ramamurthy Vishweshwara, Mahita Nagabhiru, Venkatraman Ramakrishnan