Abstract: This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Abstract: The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock signal coincident with valid trace data, and the trace receiver acknowledges the data by a change in state of an acknowledge signal. This enables generation of the next trace data point.

Abstract: A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate.

Abstract: A system and method is provided for providing a deadband switching time delay. One embodiment of the present invention includes a switching regulator system. The switching regulator system includes a control circuit configured to alternately activate a high-side power switch and a low-side power switch of the switching regulator system. The switching regulator system also includes a switching delay element configured to provide a switching deadband associated with a logic state transition delay of at least one of the high-side power switch and the low-side power switch, the delay element comprising a programmable coarse delay element to provide a course delay amount and a programmable fine delay element to provide a fine delay amount.

Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: An RFID transponder is provided which includes an automatic gain control (AGC) stage for amplifying a radio frequency (RF) signal and for providing an amplified RF signal. The AGC stage has a control signal indicating an increase of the amplitude of the RF signal. A demodulator is coupled to receive the amplified RF signal for demodulating the amplified RF signal. The demodulator provides a data signal. A burst detector is coupled to receive the control signal of the AGC stage and adapted to provide a start signal in response to a change of the control signal. A wake pattern detector is coupled to receive the data signal and the start signal. The wake pattern detector is adapted to detect a predefined wake pattern in the data signal after having received the start signal and to issue a wake signal if the predefined wake pattern is detected for switching the RFID transponder from a first operating mode into a second operating mode having higher power consumption than the first operating mode.

Abstract: The present invention relates to an outer dome configured to provide protection and optical correction to a system of projection optics and the output thereof. More particularly, an optical projection system having an optical offset of greater than 100% is comprised within a projector housing having an outer dome comprised of an optically active material mounted onto an opening approximately coinciding with the optical projection system's exit pupil. The outer dome is configured to be decenterized from the exit pupil (e.g., the center of the dome is offset from the exit pupil in one or more of an x, y, and z direction) such that it provides optical correction to a projected image. Therefore, an outer dome is configured to provide protection to optical elements provided therein and improvement of projected image quality (e.g., reduced image distortion, reduced aberration).

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate intervals. In one embodiment, a first data rate is determined for a first carrier-number mode that is to utilize a first bit table, a second data rate is determined for a second carrier-number mode that is to utilize dual bit tables, a third data rate is determined for a third carrier-number mode that is to utilize a second bit table during a FEXT interval, and a modem is configured to transmit using the mode having a highest data rate.

Abstract: A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface of a substrate. The liquid chemical is evaporated, leaving the contaminant on the surface. The contaminant is concentrated in a scanning solution, which is then evaporated to form a residue. A concentration of the contaminant in the residue is determined.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.

Abstract: An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs predistortion data to generally linearized the power amplifier. To generate this predistortion data, an indirect learning circuit and a direct learning circuit can be employed. The indirect learning circuit is generally coupled to the amplifier circuit so that it can iteratively adjust predistortion data during an indirect learning mode until convergence is reached. The direct learning circuit is generally coupled to the amplifier circuit and the indirect learning circuit and that receives the input signal so that the predistortion data can be copied to the direct learning circuit from the indirect learning after convergence is reached and so that the direct learning circuit can adjust the predistortion data during a direct learning mode.

Abstract: The invention provides a switching power supply device that can restrain the variation in the ripple of the output voltage corresponding to the variation in the input voltage and a control device thereof. When output voltage Vout is higher than a target value, switching converter circuit 10 is set to a second state (a state of discharging the power stored in inductor L1 to terminal To). When output voltage Vout is lower than the target value, switching converter circuit 10 is set to a first state (a state of storing the power input from terminal Ti in inductor L1) for a prescribed period of time and is then returned to the second state. Also, when the current flowing through inductor L1 exceeds a threshold value, switching converter circuit 10 is set to the second state.

Abstract: Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals.

Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.

Abstract: An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and the amplifier is adapted to receive an audio signal. Each differential amplifier amplifies the difference between an output voltage from the output node with a reference voltages. The FETs are coupled in series with one another between a first and a second voltage, and each FET receives an output from at least one of the differential amplifiers. Additionally, the intermediate node is coupled to a node between at least two FETs.