Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: This invention is a new approach for the image watermarking in the wavelet transform domain based on sequency of the host and watermark image. For each sub-band a first transform level of the host image is thresholded and binarized. Sequencies of thresholded and binarized data host image are compared with sequencies of the discrete wavelet transformed watermark image to form a watermarking sequency mask. The watermarked wavelet domain data is formed by combining data elements of the discrete wavelet transformed host image with corresponding data elements of the wavelet transformed watermark image as filtered by the watermarking mask. A reverse process can extract the watermark with a high degree of accuracy even after attack upon the watermarked host image.

Abstract: A detector and detection method for identifying unknown chemical solutions following chemical spills includes a specific gravity detector including a detector column having an inlet end operable to collect a sample of a solution, wherein the detector column is formed of an optically transparent material to allow visual observation of the sample in the detector column. At least a first plurality of specific gravity floats including a first specific gravity float is located and moveable within the detector column, wherein the first specific gravity float has a density to float in liquids having a specific gravity of greater than a first density level. At least a second specific gravity float is located and moveable within the detector column, wherein the second specific gravity float has a density to float in liquids having a specific gravity greater than the first density level. A sample of an unknown solution from a site of a chemical spill is introduced into the detector column.

Abstract: A packaged integrated circuit (IC) (100) includes a first substrate (110) including a first plurality of layers and first circuit coupling features (112) at an upper surface of the first substrate (110). The first plurality of layers include a first electromagnetic interference shielding layer (132). The packaged IC also includes a second substrate (106) having an upper surface attached to a lower surface of the first substrate (110) by an electrically conductive adhesive material (136). The second substrate (106) includes a second plurality of layers and a second circuit coupling feature (108) at a lower surface of the second substrate (106). The first plurality of layers includes a second EMI shielding layer (134). The packaged IC further includes a functional die (124) disposed between the first (110) and the second (106) substrates and functionally coupled to the first (112) and/or the second (108) circuit coupling features.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1810) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: An apparatus is provided. The apparatus comprises a first current source and a second current source that charge and discharge a capacitor. Coupled between the capacitor and the second current source is a switch that can be actuated and deactuated by a controller. Preferably, the controller is coupled to the capacitor and receives a first threshold voltage and a second threshold voltage so that it can actuate the switch if the voltage across the capacitor is greater than the first threshold voltage and deactuate the switch if the voltage across the capacitor is less than the second threshold voltage. Additionally, there is a comparator that is coupled to the capacitor that compares the voltage across the capacitor to a reference voltage, and there is a a multiplexer that is coupled to the capacitor and that is coupled to the comparator.

Abstract: In accordance with one embodiment of the present disclosure, a semiconductor substrate includes complementary metal-oxide-semiconductor (CMOS) circuitry disposed outwardly from the semiconductor substrate. An electrode is disposed outwardly from the CMOS circuitry. The electrode is electrically coupled to the CMOS circuitry. A resonator is disposed outwardly from the electrode. The resonator is operable to oscillate at a resonance frequency in response to an electrostatic field propagated, at least in part, by the electrode.

Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.

Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.

Abstract: A method and apparatus for automatic white balancing of an image. The method includes retrieving scene analysis of the image, determining at least one of the type of the scene and a scene content map utilizing the scene analysis of the image, performing scene adaptive white balance, if overall scene category type is used, perform white balance by applying global R, G, B gains optimized for the global scene type, and if scene segmentation map is used, perform locally adaptive white balance by applying an R, G, B gain map optimized for each scene content.

Abstract: A stable, high-speed, high-efficiency constant voltage is provided without a complicated, large-scale, high-cost phase compensation circuit over a wide range of operating conditions. This voltage buck-boost switching regulator consists of a pair of voltage reducing transistors, a pair of voltage boosting transistors, inductance coil, output capacitor and controller. The controller has the following parts for performing PWM control of constant voltage for voltage reducing transistors and voltage boosting transistors: an output voltage feedback circuit, an inductor current sense circuit, a variable sawtooth wave signal generator, switching controllers, and a voltage boosting driver.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface of a spatial light modular to an image field using a projection system; capturing light from the image field using the projection system, the projection system directing at least a portion of the captured light to the spatial light modulator; and directing at least a portion of the received captured light to an image capture system using the spatial light modulator.

Abstract: A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as Ethernet impairments, including Ethernet 1000Base-T impairments. Various interference impairments include echo cancellation, NEXT cancellation and/or other interference detection or cancellation, etc. The hardware requirements of the interference impairment cancellers are reduced by sharing filter taps among the cancellers. In a first embodiment, the taps from a unified filter tap bank are shared across all the interference impairment cancellers for all four channels and over all ports. In a second embodiment, a portion of the taps of each filter are shared wherein each canceller comprises a fixed filter tap portion and a shared filter tap portion. A tap allocation algorithm assigns taps to those cancellers that need them the most. A canceller configuration is selected that yields maximal interference mitigation and the taps are allocated accordingly.

Abstract: This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Abstract: According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate. The disclosed methods can be incorporated into, for example, altPSM, attPSM, and binary lithographic method for making semiconductor devices. a method of forming a semiconductor device is provided. The exemplary methods can include defining a plurality of first features and at least one ghost feature on a photosensitive layer by exposing a first mask to a light, wherein the first mask comprises a plurality of phase shift areas that change a phase of the light. A portion of a layer disposed under the photosensitive layer can be removed by etching to form the plurality of first features and the at least one ghost feature. One or more structures not requiring phase shifting can then be defined on the photosensitive layer by exposing a second mask to the light, wherein the second mask removes the at least one ghost feature.

Abstract: System and method for computing coefficients for color correcting rendered colors used in displaying images. A preferred embodiment comprises measuring color values of light output for a display system, receiving color values of desired colors, and computing a color correction matrix based on the measured color values and the input color values. The color correction matrix may be used to modify color commands to a light engine of the display system. The modifications to the color commands permit the storage and use of a set of color commands designed for a reference display system, simplifying display system design and manufacture.

Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t).

Abstract: The trace interface and the trace receiver may be synchronized by the trace receiver controlling the pace of trace generation. The interface generates a clock signal coincident with valid trace data, and the trace receiver acknowledges the data by a change in state of an acknowledge signal. This enables generation of the next trace data point.