Abstract: A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter.

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract: A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.

Abstract: Methods and apparatus for higher-order correction of bandgap voltage references are disclosed. An example bandgap voltage reference circuit disclosed herein comprises a bandgap voltage generation circuit comprising a first resistor, the bandgap voltage generation circuit configured to generate a proportional-to-absolute-temperature current to drive the first resistor to produce a first voltage, the first voltage contributing to an output bandgap voltage, and a first correction circuit electrically coupled to the first resistor and configured to provide a first correction current, the first correction circuit comprising a first nonlinear device configured to generate the first correction current only within a first temperature range, the first correction current decreasing with increasing temperature, the first correction current to drive the first resistor to increase the first voltage only within the first temperature range.

Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

Abstract: A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial bank. An indicator is received by the serial bank. A determination is then made as to whether the indicator was received by the serial bank prior to completion of the outputting of the register values. If the indicator was received prior to completion of the outputting of the register values, the register values are loaded into the serial bank from the readback bank.

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract: A method of forming an electronic device includes providing a patterned lower metal layer over a substrate and a first sacrificial layer there between. A second sacrificial layer is formed over the metal layer, and a portion thereof is removed. A third sacrificial layer is formed over the second sacrificial layer, and an upper metal layer is formed over the third sacrificial layer. A portion of the upper metal layer is removed, and the first, second and third sacrificial layers are removed.

Abstract: An electronic device substrate handling system. The system comprises an electronic device fabrication tool and a mechanical handling structure. The fabrication tool is configured to hold at least one substrate on a mounting body of the tool. The mechanical handling structure is configured to actuate the substrate such that the substrate is transferred to or from the mounting body. The system further comprises a vibration monitor coupled to at least one of the mechanical handling structure, or, the tool. The vibration monitor is configured to measure vibrations of the mechanical handling structure, or, the tool, while said mechanical handling structure is actuating said substrate. The vibration monitor is also configured to convert the measured vibrations into a time-dependent electrical signal.

Abstract: A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding operand is to be treated as signed or unsigned. An extend bit is appended to each operand to provide extended operands, where the extend bit is the most significant bit of the corresponding operand if type data indicates that the operand is signed, and the extend bit is a logic zero otherwise. The extended operands are multiplied using a signed multiplication operation to provide the result. Overflow detection is done in parallel to the multiply operation, thus moving overflow-detection logic from the timing-critical path from the multiplier block's input to its output. The throughput performance of the multiplier unit is improved as a result.

Abstract: This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.

Abstract: Systems and methods for efficient transmission of packets within a network communication device are described herein. Some illustrative embodiments include a network communication device that includes a plurality of ports (each port configured to communicate with one or more network devices), and a bus coupling the plurality of ports to each other (the bus providing a shared path for one or more bus transfers originated by a first port of the plurality of ports, and the one or more bus transfers including information). The bus includes a plurality of port map bits, a port map bit of said plurality of port map bits corresponding to a second port of the plurality of ports. The second port is configured to forward the information to the one or more network devices if the port map bit is asserted.

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract: An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is adapted to receive an analog input signal and to output an amplified signal. The converter is coupled to the sample and hold circuit and that converts the amplified signal to a digital signal. The controller is coupled to the converter and that receives the digital signal. The controller includes a plurality of voltage ranges, wherein each voltage range is associated with a current value, and the controller compares the digital signal to at least one of the voltage ranges to output at least one of the current values. The adjustable current circuit is coupled to the sample and hold amplifier and to the controller so that the adjustable current circuit provides a generally constant operating current that corresponds to the current value output from the controller.

Abstract: An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least a portion of a loop; the wire ends (104a) are connected to the chips. The assembly is attached to a substrate (103), which may be a leadframe. The device may be encapsulated in molding compound (140) so that the inductor can double as a heat spreader (111c), enhancing the thermal device characteristics.

Abstract: Internal servo loop circuitry is included on the same chip (10C) with an ADC (10B). Automatic test equipment (12) operates with the internal servo loop circuitry and external servo loop circuitry (1B) to test the ADC. The internal servo loop circuitry includes a target register (14), a digital comparator (18), and a crossover counter (22). An integrator (32) responsive to the digital comparator (18) produces an input signal (Vin) to the ADC, which generates a corresponding digital output sample (Dout). The comparator compares the output sample with a target code in the target register and causes the direction of the input signal to reverse each time the digital output sample crosses over the target code. The counter causes a voltmeter to measure a transition voltage value of the input voltage after a predetermined number of crossovers.