Abstract: The buffer circuit includes a first transistor MP1 having a first end coupled to an output node N2 and a control node coupled to an input node N1; a second transistor MN2 coupled to a second end of the first transistor MP1; a third transistor MN1 coupled to the second transistor MN2 such that a current in the third transistor MN1 is mirrored to the second transistor MN2; a first sense device MP3 coupled to the output node N2; a first current source I2 coupled to the output node N2; a second current source I1 coupled to the third transistor MN1; a second sense device MP2 coupled to the third transistor MN1; and a bipolar device Q1 coupled to the output node N2 and having a base coupled to the second end of the first transistor MP1.

Abstract: A method of packing electronic devices and an apparatus thereof are disclosed herein. The method allows for usage of solder materials with a melting temperature of 180° C. or higher, such as from 210° C. to 300° C., and from 230° C. to 260° C., so as to provide reliable and robust packaging. This method is particularly useful for packaging electronic devices that are sensitive to temperatures, such as microstructures, which can be microelectromechanical devices (MEMS), such as micromirror array devices.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is fabricated on the substrate. A hinge layer 13 is spaced above the addressing layer 12 by an air gap. A mirror layer 14 is spaced over the hinge layer 13 by a second air gap. The hinge layer 13 has a hinge 13a under and attached to the mirror 14a, the hinge 13a permitting the mirror 14a to tilt. The hinge layer 13 further has spring tips 13c under the mirror 14a, which are attached to the addressing layer 12. These spring tips 13c provide a stationary landing surface for the mirror 14a.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller is in communication with the fuse ROM and one or more external devices that are configured to request one or more words that reside in the fuse ROM from the electronic fuse controller. At least one security register includes indication bits that provide an indication whether security bits have been obtained for a respective block of memory of the fuse ROM after a power down and power up cycle. The electronic fuse controller provides the requested word if an indication bit associated with the block of memory is set.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.

Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

Abstract: The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.

Abstract: A method and apparatus for white balancing. The method comprising estimating the color temperature of at least a portion of the image, wherein the color temperature estimation algorithm is based on computing histogram correlations of at least a portion of at least one reference image and at least a portion of at least one target image, and correcting the white balance of at least a portion of the image utilizing the estimated color temperature.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: A method and apparatus for a projection display system includes a spatial light modulator and a volume illumination hologram. The spatial light modulator comprises a digital micromirror device, and the projection system includes a laser light source to produce a sequence of collimated, colored, light beams for the illumination hologram. Waste light produced by the spatial light modulator is transmitted to the illumination hologram, and the illumination hologram emits waste light from at least one of its edges. Waste light emitted from an edge of the illumination hologram is absorbed by a light sensor to control the intensity of the light beams. A projection focusing element is mounted proximate a side of the illumination hologram to focus the image beam from the spatial light modulator for viewing. A projection hologram is interposed between the side of the illumination hologram and the projection focusing element to manage waste light.

Abstract: A disk drive controller including a differential voice coil motor control function is disclosed. The differential voice coil motor control function includes an on-chip compensation network for the inner control loop, including a resistor formed of one or more MOS transistors connected in series. The gate of the MOS transistors in the compensation network is driven with a bias voltage based on a tuning current, where the tuning current is derived so that it varies with process and temperature variations of the integrated circuit, for example with variations in an on-chip capacitor. The on-chip compensation network can be tuned with sufficient precision to properly compensate the inner control loop to provide the desired frequency response in driving the voice coil motor in the disk drive.

Abstract: A method of fabricating a micromechanical device. Several of the micromechanical devices are fabricated 20 on a common wafer. After the devices are fabricated, the sacrificial layers are removed 22 leaving open spaces where the sacrificial layers once were. These open spaces allow for movement of the components of the micromechanical device. The devices optionally are passivated 24, which may include the application of a lubricant. After the devices have been passivated, they are tested 26 in wafer form. After testing 26, any surface treatments that are not compatible with the remainder of the processing steps are removed 28. The substrate wafer containing the completed devices receives a conformal overcoat 30. The overcoat layer is thick enough to project the micromechanical structures, but thin and light enough to prevent deforming the underlying micromechanical structures.

Abstract: One embodiment of the invention includes an amplifier system. The amplifier system comprises an amplifier stage configured to receive an input signal at an amplifier input and to provide an amplified output signal. The amplifier system also comprises a programmable input impedance stage comprising a plurality of transconductance stages. At least one of the plurality of transconductance stages can be selectively activated based on a selection signal, the at least one of the activated transconductance stages providing current through the amplifier input that adjusts an impedance associated with the amplifier input based on the amplified output signal.

Abstract: Color filter array demosaicing as is useful in digital cameras, still and video, using a single sensor includes blending of directional and non-directional interpolations. Directional interpolation uses edge detection with lowpass filtering with neighboring pixels for erroneous detection correction.