Abstract: A mobile device, such as a smart phone, is provided with a camera. Digital content displayed on display screen of the mobile device may be manipulated in response to natural movements of the mobile device by a user. Motion of the mobile device is detected relative to a nearby textured surface by analyzing images of the textured surface. The displayed digital content is manipulated in response to the detected motion of the mobile device.

Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

Abstract: The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a serial scan chain. In this invention the serial chain is connection reuses logic between slave latches on bit n and master latches on bit n+1. This reuse reduces the number of transistors required to implement the multi-bit register. This reduction in the number of required transistors enables a consequent reduction in integrated circuit area required, thereby reducing manufacturing cost. Alternatively, the area saved using this invention may be used for other purposes. This could increase the value of the corresponding integrated circuit without increasing manufacturing costs.

Abstract: A quadrature voltage controlled oscillator (QVCO). The QVCO includes a first node for providing a first quadrature signal, a second node for providing a second quadrature signal, a third node for providing a third quadrature signal, and a fourth node for providing a fourth quadrature signal. The QVCO further includes a first coil connected between the first node and the second node and a second coil connected between the third node and the fourth node. The first coil and second coil are positively magnetically coupled.

Abstract: For reducing a delay from panning a camera system, an estimate is received of a physical movement of the camera system. In response to the estimate, a determination is made of whether the camera system is being panned. In response to determining that the camera system is not being panned, most effects of the physical movement are counteracted in a video sequence from the camera system. In response to determining that the camera system is being panned, most effects of the panning are preserved in the video sequence, while concurrently the video sequence is shifted toward a position that balances flexibility in counteracting effects of a subsequent physical movement of the camera system.

Abstract: One or more waveform generators impose an input waveform across touch sensor components. Phase shift detection logic measures a phase shift between the input waveform and an output waveform component associated with each waveform generator appearing across a touch sensor component. Amplitude ratio detection logic measures an output-to-input waveform magnitude ratio associated with each waveform generator. Translator logic converts the phase shift(s) and optionally the output-to-input waveform magnitude ratio(s) to capacitance values. Validation logic compares the resulting capacitance values to each other to determine consistency and validity during a particular waveform sampling time. The phase shift detection logic and the amplitude ratio detection logic are optionally implemented with discrete Fourier transform logic which includes narrow-band filtering to exclude electromagnetic interference frequency components from touch sensor signal measurements.

Abstract: A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, Rfb, and feedback capacitor, Cfb, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R2 and R2?, and wherein the other side of the feedback capacitor is coupled between R2? and the output of the first amplifier, R2 is connected to Vbias from one side and Rfb and R2? from the other, R2? is connected to Rfb and R2 from one side and Cfb and output of the first amplifier from the other side, another resistor, R1, is connect to the output of the first amplifier, Cfb and R2? from one side and R1?, yet another resistor, and input of amp2 from the other, a second amplifier, Amp2, is connected to the R1 and R1? at one input and 1.

Abstract: A communication system includes a receiver for decoding data having three states of ?1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The powerdown mechanism is isolated to just the asynchronous bridge implemented between the master and the interconnect with a basic request/acknowledge handshake between the master subsystem and the asynchronous bridge.

Abstract: A system is provided for transmitting sub-terahertz electro-magnetic radio frequency (RF) signals using a dielectric waveguide (DWG) having a dielectric core member surrounded by dielectric cladding. An RF transmitter is coupled to an antenna located on a first substrate, in which the antenna is adjacent an edge of the substrate. The first substrate is mounted on a second substrate. A conductive reflector plate is formed on the top surface of the second substrate. An end of the DWG is mounted on the second substrate over the reflector plate such that an exposed face of the core member at the end of the DWG is adjacent the antenna. The core member at the end of DWG forms an angle of inclination with the second substrate in which the angle is in a range of approximately 10-30 degrees.

Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.

Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.

Abstract: Circuits for controlling a plurality of LEDs connected in series are disclosed herein. The circuit includes a plurality of switches, wherein each switch is connectable between the anode and cathode of one of the plurality of LEDs. Each of the switches has a first state wherein current does not pass through the switch and a second state wherein current passes through the switch. The circuit also includes an input for receiving data to program the switches and a data line for transferring data between a circuit controlling second LEDs that are connected in parallel with the first LEDs and the circuit. In addition, the circuit includes a data output for transferring data to other circuits controlling third LEDs that are connected in series with the first LEDs.

Abstract: A communication device, for use in a communication network, provides value-added information to a user of the communication device. The communication device includes a transceiver, operable to transmit and receive communications over the communication network, and a processor. The processor is operable to facilitate detecting context information representative of an environment in which the communication device is operated, detecting content information of a multi-directional communication stream by identifying significant words in the communication stream, encoding the detected context and content information as meta-information, transmitting the meta-information as a request for value-added information, receiving value-added information in response, and providing the value-added information to the user of the communication device. A method for providing value-added information to a user of a communication device and a communication system for providing value-added information are also disclosed.

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract: An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The via-first process may be a partial-via-first process or a full-via-first process. A trench mask for a wide interconnect line which is at least twice as wide as a dual damascene via in the wide interconnect line may have a dielectric slot adjacent to the dual damascene via. The dual damascene via is laterally separated from the dielectric slot by no more than half a width of the dual damascene via.

Abstract: A time slot assignment arrangement for ultralow power devices in a wireless communication network is disclosed. The time slot assigned to ultralow power device wakeup frame is identified as ultralow power timeslot using various indicators. The ultralow power timeslot is assigned as contention based timeslot allowing ultralow power devices in the wireless network to extend the interval for synchronizing with the network overcoming the short synchronization interval requirements of wireless communication network resulting in significant improvement in battery life by preserving the power needed for frequent synchronization with the wireless communication network.

Abstract: An optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer. The cavities are etched into the bonded interposer/window wafer pair using the anti-reflective coating of the window wafer as an etch stop. After formation of the cavities, the bonded interposer/window wafer pair is bonded peripherally of die areas to the MEMS device wafer, with die area micromechanical elements sealed within respectively corresponding ones of the cavities.