Abstract: A current source generates, with high efficiency, a current that is substantially constant over a wide range of output voltages. This current is injected into the first end of a series-connected string of LEDs, with the second end of the string connected through a resistor to ground. The voltage developed across this resistor, which is a measure of current flow in the series string, is fed back to the current source, wherein feedback maintains nearly constant current output over a wide range of output voltages. A field effect transistor (FET) is placed in parallel with each LED in the string. A level shift gate driver couples a pulse width modulated control signal to the gate of each FET. With the FET being coupled across a particular LED, the LED can be bypassed when the FET is actuated or receive current when the FET is deactuated. By modulating the duty cycle of each FET, the brightness of each associated LED may be varied smoothly over its full range.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A system and method for measuring a temperature in at least one energy storage unit. The system includes at least one temperature sensor thermally coupled to the at least one energy storage unit, and a battery management controller in communication with the at least one temperature sensor. The battery management controller is configured to process a temperature of the at least one energy storage unit to obtain an internal temperature in the at least one energy storage unit.

Abstract: Disclosed herein is a dielectric microstructure with a substantially unit dielectric constant K for use in microelectromechanical systems.

Abstract: A system and method for improving bit-loading in discrete multitone (DMT)-based digital subscriber line (DSL) modems. In one embodiment, the system includes: (1) a model generator configured to generate a model containing a calculated total bit loading for an assumed gross coding gain and estimated total bit loadings for a other plurality of assumed gross coding gains and (2) a bit loader associated with the model generator and configured to load bits in accordance with the model.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: The present invention provides a method for removing sacrificial materials in fabrications of microstructures using a selected spontaneous vapor phase chemical etchants. During the etching process, an amount of the etchant is fed into an etch chamber for removing the sacrificial material. Additional amount of the etchant are fed into the etch chamber according to a detection of an amount or an amount of an etching product so as to maintaining a substantially constant etching rate of the sacrificial materials inside the etch chamber. Accordingly, an etching system is provided for removing the sacrificial materials based on the disclosed etching method.

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the “clock-to-Q period”) is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal.

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

Abstract: A holdover circuit is configured with a holdover capacitor, preferably an aluminum electrolytic capacitor, to provide uninterruptible operation for an electrical load operable over a limited range of input voltage during brief power interruptions. The holdover circuit includes a switching regulator configured with two active switches that are controlled with complementary duty cycles to charge and discharge the holdover capacitor at a voltage higher than the voltage of the load. The controller for the switching regulator may be configured to regulate the voltage of the holdover capacitor at a voltage proportional to the load voltage or at a constant voltage. The controller for the switching regulator is configured to operate in different modes during normal powered operation and during holdover.

Abstract: A modular instance-aware event-driven test framework is described. It includes an event-driven test framework, a transition-graph test model for the event-driven text framework, an instance-aware event-driven test framework built on said event-driven test framework and a transition-graph test model for said instance-aware event-driven test framework built on said transition-graph test model.

Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.

Abstract: A method and an apparatus for compressing image data. The method includes dividing a line of an image into equal length fragments to form a coding unit, transforming and performing entropy coding to the coding unit, and compressing the image data based on the transformed entropy coded coding unit.

Abstract: A high data width accelerator, comprising computer instructions for calculating at least a portion of a trace-back during a trellis computation, wherein the calculation allows faster trace-back

Abstract: A delay applied to a turn-on time for a high side switch in a switch mode power converter prevents oscillation between continuous and discontinuous conduction modes under light load conditions. The delay equalizes turn-on time for a high side switch with respect to continuous and discontinuous modes, so that turn-on time is not treated differently between the different modes. The delay value can be set for be equivalent to a propagation delay through a driver for a low side switch, in addition to a turn-off time for the low side switch. The addition of the delay element tends to maintain the switch mode power converter in a discontinuous mode under light load conditions and avoids oscillation between discontinuous and continuous conduction modes.

Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: A method and apparatus for image enhancement. The method includes measuring local activity of at least a portion of the image, utilizing the measured local activity for determining gradient at least a portion of the image, utilizing the determined gradient to enhance edges in at least a portion of the image, and utilizing the measured local activity of at least a portion of the image to limit edge enhancement intensity value range and to prevent halo in at least a portion of the image.