Abstract: Various apparatuses and methods for synchronizing time stamps are disclosed herein. For example, some embodiments of the present invention provide apparatuses for synchronizing a coarse time stamp with a fine time stamp. Such apparatuses include an event signal input, a clock input, a coarse time stamp generator having an input connected to the clock input, and a fine time stamp generator having a first input connected to the clock input, a second input connected to the event signal input, and a synchronization signal output. The apparatuses also include a synchronizer having a first input connected to the clock input, a second input connected to the event signal input, a third input connected to the synchronization signal output and an output connected to the coarse time stamp generator. The synchronizer is adapted to synchronize the coarse time stamp generator to the fine time stamp generator based at least in part on the synchronization signal output.

Abstract: A controller for a DC/DC converter is provided. The controller comprises an error circuit, control logic, a high side driver, a low side driver, and an interface circuit. The error circuit is coupled to a feedback terminal so as to receives a feedback signal and is coupled to the control logic. The high side driver is coupled to the control logic and to a first output terminal so as to provide a first actuation signal, and the low side driver is coupled to the control logic and to a second output terminal so as to provide a second actuation signal. The interface circuit is also coupled to the control logic, including a first, second, and third voltage source, interface comparators, and current limited amplifier.

Abstract: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

Abstract: A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

Abstract: A device is protected from induced or unexpected current spikes or surges, by receiving the current spikes through a conducting wire. The conducting wire is placed adjacent to a parallel conducting wire having opposing current flow. Magnetic fluxes in either conducting wire create induced currents that reduce the current in the other conducting wire.

Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract: A semiconductor device employs a support structure to mitigate damage to dielectric layers having a low dielectric constant (k). The semiconductor device includes at least one inter-level dielectric layer (ILD) comprising a material having a low dielectric constant (k), and at least one support structure disposed within the low-k dielectric layer. The support structure mitigates damage of the semiconductor device by providing a mechanically stable interface between two layers in the semiconductor device.

Abstract: The present application is directed to a method for determining photolithography focus errors during production of a device. The method comprises providing a substrate and forming a photoresist pattern on the substrate. The photoresist pattern comprises a device pattern and one or more blocking scheme patterns. The process further comprises performing a device manufacturing process using the photoresist pattern as a mask to form sensor windows on the substrate. One or more focus error sensors are formed in the sensor windows. Focus errors are determined using the focus error sensors. Other embodiments of the present application are directed to wafers comprising one or more focus error sensors positioned in sensor windows.

Abstract: When an APC selection signal FA is set to H level to start an APC operation, a monitor voltage VA is immediately generated from a monitor voltage generating circuit 16A, and an error voltage VEA corresponding to the difference between the monitor voltage VA and a reference voltage VP is output from an error amplifying circuit 18A. However, until the monitor voltage VA reaches the vicinity of the reference voltage VP, a S/H circuit 20A is held in a hold mode, and a laser diode LDA is driven at a switching current ISA with the same current value as before the APC operation start. After the monitor voltage VA reaches the vicinity of the reference voltage VP, the S/H circuit 20A is switched to a sampling mode, and a feedback control operation of a closed loop is started.

Abstract: A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to a node to be compensated; a first resistance coupled between an output of the amplifier and the replica circuit; a second resistance coupled between the output of the amplifier and the node to be compensated; and wherein the replica leakage current is subtracted from the node to be compensated.

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract: Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control with fast adaptation and minimal speech distortion, echo cancellation updated in the frequency domain with stepsize optimization and smoothed spectral whitening, and echo suppression with adaptive talking-state transitions.

Abstract: The present disclosure describes systems and methods for driving light emitting diodes (LEDs). At least some embodiments include an LED driver system that includes a power supply, a plurality of current sources (each current source coupled between a common return resistor and one of a plurality of branches of series coupled LEDs, and each branch coupled between a corresponding current source and the power supply), and control logic coupled to the current sources (the control logic capable of controlling the current flow through each current source). Each of the current sources allows current to flow during one of a plurality of substantially non-overlapping time periods within a repeating time interval, each current source allowing current to flow during a different time period. The magnitude of the current flowing through each current source is substantially the same and is regulated based upon a feedback voltage across the common return resistor.

Abstract: A method is provided for dramatically improving communications data throughput on embedded systems and reducing the load on the operating system and central processing unit by moving the network protocol logic nearer to the underlying communication hardware, and utilizing the communication processor hardware abstraction layer (CPHAL) concepts. This movement of the network protocol logic allows leveraging the CPHAL data structures, which are tightly bound to the communication packets being processed. The decision making is made just above the CPHAL layer; and the CPHAL data structure is preserved. Copying data is avoided by manipulating of pointers within the CPHAL buffer.

Abstract: According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.

Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.