Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the target that lies within a sensing domain area to change. A portion of the target always lies within at least one of the sensing domain areas of the plane.

Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.

Abstract: A device is configured for identifying a direction of a sound. The device includes a controller comprising circuitry. The circuitry is configured to receive a first output from a first input device and a second output from a second input device. The circuitry is also configured to add a delay to the second output. The circuitry is also configured to compare the first output to the delayed second output in a plurality of directions to form a comparison. The circuitry is also configured to identify a number of null directions of the plurality of directions where a set of nulls exists based on the comparison.

Abstract: A method for adapting a mixed signal Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) using pivot taps and monitor taps is disclosed. The method includes, for a given IIR path for a received signal, updating gain of the given IIR path using a respective pivot tap error-data correlation with a first Least Mean Square (LMS) update equation; and updating a time constant of the given IIR path using a respective monitor tap error-data correlation with a second LMS update equation.

Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

Abstract: A key fob includes a transceiver to send and receive signals, a memory to store a key fob identification (KFID), and a processor coupled to said transceiver and memory. The processor is to execute, along with a pairing device, an identification (ID) authenticated key agreement protocol based on the KFID to authenticate a pairing device and to generate a common secret encryption key known only by the processor and the pairing device. The Processor receives a control unit identification (CUID) encrypted by the pairing device with the common secret encryption key, execute along with the control unit associated with the CUID an ID authenticated key agreement protocol based on the CUID to authenticate the control unit, generates a second common secret encryption key known only by the processor and the control unit, and receives an operation key encrypted by the control unit with the second common secret encryption key.

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: Systems and methods for phase alignment among multiple transmitters are described. In some embodiments, a method may include creating a loop between an RF transmitter and an RF receiver; measuring a first DC signal on the I and Q paths of the RF receiver without inserting a DC signal in the I and Q paths of the RF transmitter; measuring a second DC signal on the I and Q paths of the RF receiver while inserting a non-zero DC signal in the I and Q paths of the RF transmitter; and calculating a relative phase difference between the RF transmitter and the RF receiver using the first and second DC signals.

Abstract: A rotary encoder and rotary encoder system that provides rotation detection and generates tactile feedback using a single magnetic mechanism and without relying on mechanical detects. The rotary encoder utilizes a ring magnet attached to a knob, two Hall Effect sensors that detect movement information for the processor, and magnets that are mounted to the surface of the platform. As the knob and multipole ring magnet get rotated, the ring magnet is subjected to opposing forces due to the magnets mounted to the platform surface, causing an unstable position that is experienced as tactile feedback by the user rotating the knob. Releasing the knob snaps the magnetic ring into one of many fixed positions, thus providing further tactile feedback.

Abstract: A packaged capacitive MEMS sensor device includes at least one capacitive MEMS sensor element with at least one capacitive MEMS sensor cell including a first substrate having a thick and a thin dielectric region. A second substrate with a membrane layer is bonded to the thick dielectric region and over the thin dielectric region to provide a MEMS cavity. The membrane layer provides a fixed electrode and a released MEMS electrode over the MEMS cavity. A first through-substrate via (TSV) extends through a top side of the MEMS electrode and a second TSV through a top side of the fixed electrode. A metal cap is on top of the first TSV and second TSV. A third substrate including an inner cavity and outer protruding portions framing the inner cavity is bonded to the thick dielectric regions. The third substrate together with the first substrate seals the MEMS electrode.

Abstract: Several circuits and methods that may be implemented to enable specification support of a plurality of interface components in an IC are disclosed. In an embodiment, a circuit includes a plurality of multiplexer circuits and a control circuit. The plurality of multiplexer circuits are configured to provide a plurality of data paths and a plurality of outputs according to a set of selection signals. The plurality of data paths is configurable for at least a first mode of operation or a second mode of operation based on the set of selection signals. The first mode of operation and the second mode of operation are associated with complimentary specifications. The control circuit is coupled with the plurality of multiplexer circuits in order to control the set of selection signals of the plurality of multiplexer circuits to thereby select one of the first mode and the second mode of operation.

Abstract: An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.

Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.