Abstract: The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1 via node N1 is detected by current detection circuit 1. At bias control circuit 2, base voltage of npn transistor Q2 is regulated in such a manner that the current of npn transistor Q2 decreases in accordance with an increase in said detected current, and the current of npn transistor Q2 increases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.

Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

Abstract: An electronic device (18). The device comprises an analog (16) interface for receiving an analog waveform. The device also comprises an image screen (20) and circuitry (42) for at times displaying an image on the image screen in response to at least a portion of the analog waveform. The device also comprises a memory (48) for storing firmware code and circuitry (44, 46) for at times writing firmware code in the memory in response to at least a portion of the analog waveform.

Abstract: A method of producing an image. Image data word comprising image data bits for a portion of the image is received at a first frame rate. At least two threshold data values are selected. A first portion of the image data word is compared with the threshold data values. A second portion of said image data word is displayed at a frame rate at least two times said first frame rate. Image data based on the comparison between the first portion of the image data word and the threshold data values is displayed at a frame rate at least two times the first frame rate.

Abstract: A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the precharge node and the second switch is responsive to the one of a high or low voltage at the precharge node to control the first switch charging the precharge node. The first switch is preferably a p-channel transistor and the second switch is preferably an n-channel transistor. The circuit also includes an output terminal, an inverter coupled between the precharge node and the output terminal and feedback circuitry coupled between the output terminal and coupled to the second switch to provide the charge state of the precharge node to the second switch. The circuit further includes a pair of transistors having serially connected current paths, the serially connected current paths being coupled between the precharge node and a reference source.

Abstract: A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.

Abstract: Packetized CELP-encoded speech playout with frame truncation during silence and frame expansion method dependent upon voicing classification with voiced frame expansion maintaining phasealignment.

Abstract: A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Abstract: In accordance with the teachings of the present invention, a spatial light modulator mirror metal having enhanced reflectivity is provided. In a particular embodiment of the present invention, a light processing system includes a light source operable to provide a light beam along a light path and a spatial light modulator positioned in the light path, the spatial light modulator comprising an array of pixel elements, each pixel element comprising a deformable micro-mirror operable to reflect the light beam in at least one direction. At least a portion of each deformable micro-mirror comprises an Al—Cu alloy. A controller electrically connected to the spatial light modulator is operable to provide electrical signals to the spatial light modulator to cause the spatial light modulator to selectively deform the pixel elements, thereby selectively reflecting incident light beams along a projection light path.

Abstract: Automatic white balancing and/or autoexposure as useful in a digital camera extracts color channel gains from comparisons of image colors with reference colors under various color temperature illuminants and/or extracts exposure settings from illuminance mean, illuminance variance, illuminance minimum, and illuminance maximum in areas of an image with a trained neural network.

Abstract: Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at least one garland of closed chains of tiles. Each image includes a spanning set of these garlands. Rotation in place moves each pixel to the next location on its garland. On completion of a garland by return to the initial tile, tiles on the next garland are moved. Image rotation is complete after all the garlands have been traversed. This invention first linearized the two-dimensional tiles sliding into groups of super-pixels at contiguous locations above the image buffer. The tiles are rotated in place. The shuffled tiles are delinearized into rectangular blocks and then re-pitched if needed.

Abstract: A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906). The bond pads on the electrical device (906) are electrically connected to bond pads on the package (904) by a series of bond wires (908) through use of a well know bonding process. A vacuum source holds the package (904) against the pedestal (902) deforming the resilient strips (920) located in the rigid member (902) of the pedestal and ensuring good contact between the ground pads of the package (904) and conductive resilient members (920). The resilient members (920) are conductive and electrically connect the package grounds to a system ground (922).

Abstract: Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control with fast adaptation and minimal speech distortion, echo cancellation updated in the frequency domain with stepsize optimization and smoothed spectral whitening, and echo suppression with adaptive talking-state transitions.

Abstract: A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal device 10, the influence of the Early effect pertaining to the three-terminal device of a FET is reduced. In order to reduce the influence, control unit 30 is set for reducing the Early effect component caused by a three-terminal device. As a result, by controlling the potential of the second terminal (such as drain) of the device as a response to a first signal pertaining to the input signal received by the first terminal (such as gate) of the device, it is possible for the potential difference between the second terminal (drain) and the third terminal (such as source) of the device to be essentially constant.

Abstract: A method for determining whether a tire is in rotation is provided. A measured acceleration is compared to a first threshold after a first timer indicates that a first period has lapsed, and indication that the tire is in rotation is provided if at least one of the measured accelerations is greater than the first threshold. If an absolute difference between consecutive measured accelerations is greater than a second threshold, an indication that the tire is in rotation is also provided. Additionally, the second timer is started if the absolute difference is greater than the second threshold and if a second timer is not running, and indication that the tire is rotating is provided if the absolute difference is less than a predetermined threshold and if the second timer is running.

Abstract: An imaging apparatus is provided. The apparatus generally comprises an array and storage elements. The array includes photosensitive cells that are arranged in a plurality of columns and a plurality of rows such that each column includes a set of photosensitive cell pairs that have a shared region with a share floating diffusion region and a shared selection transistor. Also, the location of each shared region of each column is shifted by one row in each adjacent column.

Abstract: Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.

Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

Abstract: Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of the wafer. The resist mitigates the creation of contaminants, such as nitride flakes, for example, that can develop when an oxide, nitride, oxide (ONO) layer is removed from the back or in-active side of the wafer. In the absence of the resist, such flakes may migrate to the front or active side of the wafer and cause defects to form therein, which can result in yield loss.

Abstract: System and method for preprocessing a signal for transmission by a power amplifier. In a preferred embodiment a multiple input multiple output processor is coupled to a plurality of power amplifiers for transmitting a signal, where the number of power amplifiers exceeds the number of antennas. The multiple input multiple output processor performs an algorithm to optimize the output vector ensuring that the transmit power for any one amplifier is below a predetermined threshold. In a preferred embodiment a Remez optimization algorithm is performed. Alternative optimization algorithms may be used. In a preferred embodiment the processor is a single integrated circuit. A method is disclosed where a multiple output vector is produced for transmission, using an optimization algorithm to produce an output vector that ensures that for any of the power amplifiers, the transmit power is maintained below a predetermined threshold.