Abstract: A pixel array display system including an illumination source of discrete emitters with uniform emitting areas, a separate collimator in front of each emitter, and a condenser in front of said collimators which focuses collimated light from the emitters onto the pixel array. The pixel array display system does not include a light homogenizing optical element such as a light pipe. Each emitter is focused onto at least 75 percent of the pixels. A portion of the emitters which provide collimated light cones proximate to a modulated light optical cone from the pixel array may be provided reduced power in a high contrast operating mode.

Abstract: A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.

Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.

Abstract: An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas.

Abstract: A packing insert for disc-shaped objects comprising a ring and a deformable contacting portion supported by the ring and extending from a circumference of the ring. The contacting portion can comprise one or more solid portions extending from the circumference. The solid portions can define a plurality of radially arranged members separated by a plurality of void regions, where the solid portions extending radially from a circumference of the ring.

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.

Abstract: A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|<a predetermined voltage level (PVL), where the control signal activates the main comparator. A second OM is implemented when |Vin|?PVL where the main differential pair is protected by a switch from developing transient voltage input offset (VIO). Logic circuitry has logic inputs receiving outaux and outmain, and a logic output providing a decision result for the dual-comparator circuit using outmain when in the first OM and outaux when in the second OM.

Abstract: In described examples, a phase interleaver obtains (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii) a second signal indicating a voltage across an energy storage device. A voltage regulator includes multiple phase blocks collectively configured to generate the regulated output voltage. In a repeating cycle, (i) the voltage across the energy storage device is increased while the second signal is less than the first signal and (ii) in response to a determination that the second signal is greater than the first signal, the energy storage device is substantially discharged, multiple stages of a clock divider are transitioned in the phase interleaver, and a set of control signals is output from the clock divider. The control signals have a common switching frequency and a common switching period. The control signals control the phase blocks active in generating the output voltage.

Abstract: A method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.

Abstract: Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier (3,20) and an interfacing circuit (4,8,9,44), including a programmable first reactive element (C) and a second reactive element (L). Amplitude sensing circuitry (42) senses a maximum amplitude of an in-phase signal (I) or a quadrature-phase signal (Q). An on-chip first tone generation circuit (38,38A,38B,38C) generates tones for injection into the in-phase signal and the quadrature-phase signal and operates in response to frequency scanning circuitry (30) and the amplitude sensing circuitry to adjust the first reactive element (C) to calibrate the first resonant circuit to a desired resonant frequency by selectively coupling reactive sub-elements (1, 2, 4, 8 . . . ×Cv) into the first reactive element (C).

Abstract: A noise-cancelling system includes headset for generating a feedback signal for noise-cancellation in response to sound externally generated from the headset. The noise-cancellation feedback signal can also be described as a noise-cancellation “feed-forward” signal. An encoded microphone signal is generated in response to the first feedback signal. An audio generator can be used to generate a noise-cancellation signal in response to the encoded microphone signal and to generate an electronic audio signal in response to the encoded microphone signal and a first output audio signal. An audio connector is provided to couple the encoded microphone signal from the headset to the audio generator and to couple the first electronic audio signal to the headset.

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed.

Abstract: Disclosed examples include ICs and general-purpose I/O circuitry to facilitate interfacing of the IC with a variety of external circuits operating at different supply voltages, in which an integer number N supply drive circuits are individually coupled with a corresponding supply voltage node and selectively connect the corresponding supply voltage node to a general-purpose output node based on a supply drive control signal to allow programmable interfacing of individual general-purpose output pads or pins of the IC with an external circuit at the appropriate signal level.

Abstract: A method of operating a node of a network is disclosed. The method includes receiving a data frame having a header with plural addresses. The node determines if a first address of the plural addresses is an address of a descendant of the node and if a second address of the plural addresses is a parent address of the node. If so, the node changes a second address of the plural addresses to its own address in response to the step of determining. The node then transmits the data frame to at least one descendant of the node.

Abstract: A method of operating a wireless communication system is disclosed. The method includes configuring a user equipment (UE) for carrier aggregation with N serving cells, where N is a positive integer. The UE is scheduled to receive downlink data from M of the N serving cells at a first time, where M is a positive integer less than or equal to N. The UE provides uplink control information (UCI) for only the M serving cells.

Abstract: Protection circuits, USB interface integrated circuits, and methods for protecting host circuitry from USB port pin overvoltages, in which a switch is connected between a USB port pin and a middle node, and a detection circuit compares the middle node voltage with a reference voltage. A control circuit turns off the switch and turns on a clamp circuit to conduct pull down current from the middle node in response to the middle node voltage exceeding the reference voltage to mitigate overvoltage conditions on a host pin coupled to the middle node. When the middle node voltage falls below the reference voltage, the control circuit delays for a predetermined time and then turns off the clamp circuit and turns on the switch.

Abstract: Systems and methods for loudspeaker protection against excessive excursion are described. In an illustrative, non limiting embodiment, a method may include splitting an input signal into two or more signals, each of the two or more signals within a given frequency band; independently selecting between a power attenuation or an excursion attenuation for each of the two or more signals; independently applying the selected power attenuation or excursion attenuation to each of the two or more signals; combining the attenuated two or more signals into an output signal; and providing the output signal to a loudspeaker.

Abstract: USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Abstract: Example embodiments of the systems and methods of wireless USB service discovery disclosed herein provide the querying of the MAC address of devices for available services to determine the information elements provided to the querying devices based on access categories specified by the user of the querying device. Sniffing or querying of the Wi-Fi enabled devices may subsequently determine which of the MAC addresses correspond to known friends and automatically make that content accessible to those friends by including these MAC addresses in file metadata so that a device with this MAC address can subsequently access the file. Availability of this file for download may subsequently be advertised.