Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Abstract: An inductive sensing system includes multiple resonant sensors interfaced to an inductance-to-digital conversion (IDC) unit through a single channel interface. IDC establishes an IDC control loop that incorporates resonant sensors as loop filters. The IDC control loop drives resonant sensors to a system resonance state in which each resonant sensor is driven to a resonant frequency state. Each resonant sensor is configured for a nominal resonant frequency state that differentiates it from the other resonant sensors. IDC senses changes in system resonance state representative of target-sensing conditions, and responds by driving a target-sensing system resonance state. IDC converts IDC loop (resonance) control signals resulting from a target-sensing condition into sensor data as representing the corresponding target-sensing resonant frequency state as an indication of target position (proximity or range) relative to a target-sensing resonant sensor.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract: Channel state information (CSI) feedback in a wireless communication system is disclosed. User equipment transmits a CSI feedback signal via a Physical Uplink Control CHannel (PUCCH). If the UE is configured in a first feedback mode, the CSI comprises a first report jointly coding a Rank Indicator (RI) and a first precoding matrix indicator (PMI1), and a second report coding Channel Quality Indicator (CQI) and a second precoding matrix indicator (PMI2). If the UE is configured in a second feedback mode, the CSI comprises a first report coding RI, and a second report coding CQI, PMI1 and PMI2. The jointly coded RI and PMI1 employs codebook sub-sampling, and the jointly coding PMI1, PMI2 and CQI employs codebook sub-sampling.

Abstract: A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.

Abstract: A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF4) and oxygen gas (O2) into the chamber at a temperature of at least about 200° C.

Abstract: A method of operating a wireless communication system is disclosed. The method includes receiving respective downlink transmissions at N second transceivers from a first transceiver, where N is a positive integer greater than 1. The reception acknowledgement signals by the N second transceivers are combined into a single reception acknowledgement signal and transmitted to the first transceiver.

Abstract: A method of operating a wireless communication system is disclosed. The method includes receiving first and second parallel data streams. The first data stream is converted to a first frequency-domain data stream by a discrete Fourier transform (DFT) having NDFT0 size, where NDFT0 is a positive integer. The second data stream is converted to a second frequency-domain data stream by a DFT having NDFT1 size, where NDFT1 is a positive integer. The first and second frequency-domain data streams are mapped to respective subcarriers.

Abstract: An integrated circuit with copper damascene interconnects includes a thin film resistor. Copper damascene metal lines are formed in a first ILD layer. A dielectric layer including an etch stop layer is formed on the first ILD layer and metal lines. Resistor heads of refractory metal are formed in the dielectric layer so that edges of the resistor heads are substantially coplanar with the adjacent dielectric layer. A thin film resistor layer is formed on the dielectric layer, extending onto the resistor heads. A second ILD layer is formed over the dielectric layer and the thin film resistor layer. Copper damascene vias are formed in the second ILD layer, making contact to the metal lines in the first ILD layer. Connections to the resistor heads are provided by the metal lines and/or the vias.

Abstract: A method of operating a wireless communication system is disclosed. The method includes communicating by a first data frame having a first transmit time interval with a first wireless transceiver and communicating by a second data frame having a second transmit time interval different from the first transmit time interval with a second wireless transceiver. Data is transferred between the first data frame and the second data frame.

Abstract: A method of operating a wireless communication system is disclosed. The method includes receiving allocation information for a plurality of second wireless transceivers from a first wireless transceiver by one of the second wireless transceivers on a physical broadcast channel (PBCH). The one of the second wireless transceivers decodes the allocation information for the plurality of second wireless transceivers.

Abstract: A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is disposed in the primary portion of the substrate. An interconnect region is formed on a top surface of the substrate. Semiconductor material is removed from the substrate in an isolation region, which is separate from the primary portion of the substrate; the isolation region extends from the top surface of the substrate to a bottom surface of the substrate. A dielectric replacement material is formed in the isolation region. The semiconductor device further includes an isolated component which is not disposed in the primary portion of the substrate. The dielectric replacement material in the isolation region separates the isolated component from the primary portion of the substrate.

Abstract: Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data ‘1’ or ‘0’ to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Abstract: A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating capacitance value to automatically adjust a loop bandwidth of the PLL. A charge-pump DAC generates a charge-pump current of magnitude controlled by the state machine control signals. An integrator integrates the charge-pump output current to produce an integrated charge-pump output signal. The integrator has a plurality of capacitors switchably selected by control signals from the state machine to produce an integrating capacitance value. A voltage controlled oscillator (VCO) produces a PLL output frequency in response to the integrated charge-pump output signal.

Abstract: A method of operating a wireless communication system (FIG. 4) is disclosed. The method includes receiving a plurality of reference signals from a respective plurality of transceivers (402). Each, of the plurality of reference signals is measured to produce a respective plurality of channel state information (CSI) measurements (404). An aggregated channel quality indicator (CQI) is calculated from measuring the plurality of reference signals (406). The aggregated CQI is transmitted to at least one transceiver of the respective plurality of transceivers (408).

Abstract: An apparatus is provided. A polynomial register having a plurality of bits is provided, where the polynomial register is configured to store a user-defined polynomial. A transceiver is coupled to a first bus, a second bus, and the polynomial register. The transceiver includes a self-synchronous scrambler that is configured to generate a scrambled signal from a first signal using the user-defined polynomial and a self-synchronous descrambler that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.