Abstract: A back electromotive force (BEMF) zero cross may be detected in a brushless direct current (BLDC) motor that is controlled by pulse width modulation (PWM). A phase input of the BLDC motor is tri-stated during PWM periods in which the phase input conducts motor drive current, and the tri-stating of the phase input is used to determine whether a BEMF zero cross has occurred in the BLDC motor.

Abstract: A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: Stepper motor winding current regulation methods and apparatus adapt a maximum blanking period to generate an adapted blanking period that is proportional to a currently-selected current regulation set-point. Sensed winding current feedback is ignored at a current regulation controller during the adapted blanking period or during a minimum blanking period, whichever longer, to avoid attempting to track noise imposed upon a sensed winding current feedback signal at an initiation of rapid current changes di/dt. Doing so may decrease ripple in the motor winding current waveform and reduce zero-crossing distortion by decreasing overshoot of the current regulation set-point by the sensed winding current.

Abstract: A method of processing received satellite signals is provided. The method includes detecting frequency, power level, code phase and doppler frequency of a plurality of satellite signals and frequency and power level of a plurality of spurious signals. The plurality of spurious signals is ranked based on one or more ranking parameters. A first subset of the plurality of spurious signals which are ranked equal or above a threshold rank are processed through a plurality of notch filters and a second subset of the plurality of spurious signals which are ranked below the threshold rank are processed through a weeding filter.

Abstract: Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input signal, an analog detector circuit to provide a detector output signal representing a feature of the input signal, a second sampling circuit to sample the detector output signal, and a control circuit to control a sample rate or other analog front end operating parameter at least partially according to the sampled detector output signal, and to selectively enable and disable the analog detector circuit at least partially according to a model representing an expected repeating waveform of the input signal.

Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: An asynchronous analog-to-digital converter (AADC) and a method of using the AADC are shown. The AADC includes a digital-to analog-converter (DAC), a continuous-time comparator that provides an output including a digital value of the DAC and a time value, and a first and a second continuous-time summer, each connected to receive an analog differential input on a first input, to receive a differential output of the DAC on a second input, and to provide a difference between the analog input and the output of the DAC to the continuous-time comparator and to an error estimator. The continuous-time comparator provides the output responsive to the difference between the analog input and the output of the DAC being zero.

Abstract: A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract: A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order bits. The resistor ladder circuit includes a stem resistor and a branch resistor. The stem resistor has a stem resistance, and the branch resistor has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit includes a string current source, a string resistor, and a bridge resistor. The string current source is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal decoded from the low order bits.

Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.

Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

Abstract: Devices, systems and methods are disclosed for assigning unique addresses to slave devices in a system comprising a host controller and multiple slave devices connected in a daisy chain configuration. The host controller initiates the address programming protocol, resulting in address assignment commands propagating along the daisy chain to each of the slave devices. Upon receiving an address assignment, each slave device issues an updated address assignment for the neighboring downstream slave device in the daisy chain. In this manner, slave devices are uniquely addressed using a single command, such that slave devices do not require factory-programmed device addresses. Also disclosed are communication protocols that allow the host controller to communicate with each of the daisy-chained slave devices or with certain subsets of the slave devices.

Abstract: An image projector includes a digital micro device (DMD) spatial light modulator and a rotatable actuator. The rotatable actuator is disposed in a path of light reflected from the spatial light modulator. The rotatable actuator includes a first region and a second region. The first region is tilted at a first non-normal angle with respect to an axis of rotation of the rotatable actuator. The second region is tilted at a second non-normal angle with respect to the axis of rotation of the rotatable actuator. Light reflected by the spatial light modulator and passing through the first region is displaced one pixel relative to light reflected by the spatial light modulator and passing through the second region.

Abstract: Disclosed examples include methods and network devices for communicating in a wireless network, in which the device generates frequency hopping sequence y(j) having a prime number sequence length p, using cyclotomic classes in a field of p or using a baby-step giant-step algorithm, where y(0)=p?1 and the remaining sequence values y(j)=log?(j) mod (p?1). In certain examples, ?=2 and the sequence is generated without solving logarithms using one or more algorithms to conserve memory and processing complexity for low power wireless sensors or other IEEE 802.15.4e based networks using Time-Slotted Channel Hopping (TSCH) communications.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: The disclosed systems and methods emphasize driving LEDs in series and in parallel with the same LED driver chip and a single inductor. For creating overlap, the systems and methods of LED color overlap disclosed herein take advantage of the fact that green and blue LEDs have the same voltage. Thus, green and blue LEDs can be driven in parallel as needed. LED suppliers can screen parts for sufficiently close voltage matching between green and blue LEDs. This is especially true when using green LED die based on a blue die with a green phosphor. Cyan may be produced by driving a green LED and a blue LED in parallel. White may produced by driving a green LED and a blue LED in parallel and a red LED in series with this green and blue parallel pair.