Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A laser module includes a Distributed Bragg Reflector semiconductor laser light source that is operable to generate a light beam having a stabilized frequency and spatial mode. A periodically poled, nonlinear optical device is operable to receive the light beam, and frequency-convert the light beam.

Abstract: A mobile electronic device includes circuitry for contactless charging. The circuitry comprises an inductor for contactlessly receiving power and supplying the power to the mobile electronic device. A control stage coupled to the inductor and is adapted to control a supply of power received by the inductor to the load to regulate a load current such that a supply voltage is maintained above a predetermined level.

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract: A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word line driver coupled to word lines of the SRAM array and configured to operate at a word line driver voltage and (2) a bit line precharge circuit coupled to bit lines of the SRAM array and configured to precharge the bit lines to a precharge voltage substantially lower than the word line driver voltage.

Abstract: A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC quantization noise shaping scheme is effective to reduce the TDC quantization noise to acceptable levels especially in the case of integer-N channel operation. The mechanism monitors the output of the TDC circuit and adaptively generates a dither (i.e. delay) sequence based on the output. The dither sequence is applied to the frequency reference clock used in the TDC which adjusts the timing alignment between the edges of the frequency reference clock and the RF oscillator clock. The dynamic alignment changes effectively shape the quantization noise of the TDC. By shaping the quantization noise, a much finer in-band TDC resolution is achieved resulting in the quantization noise being pushed out to high frequencies where the PLL low pass characteristic effectively filters it out.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and a second feature on a substrate by exposing a first mask to a first beam, wherein the second feature is disposed adjacent to the first feature, exposing a second mask to a second beam, and removing the second feature from the substrate.

Abstract: A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.

Abstract: The display system separates reflected and transmitted light from a color wheel of the display system; and modulates the separated reflected and transmitted light components using separate spatial light modulators so as to achieve high brightness.

Abstract: In a method and apparatus for rapidly recovering an improved amplifier from an overload condition, a cascode amplifier (CASA) having a pair of inputs and an output is coupled to an overload recovery circuit (ORC). The pair of inputs is coupled to receive a differential input signal. A deviation in the differential input signal that is greater than a threshold causes a deviation in a current provided to at least one transistor included in the CASA. The deviation in the current causes the CASA to operate in an overload condition (OC). The ORC includes a makeup current circuit operable to generate an overload current in response to the OC and a controller operable to control a voltage at the output during the OC. The controller coupled to the makeup current circuit provides the overload current to the CASA to enable the rapid recovery from the OC.

Abstract: A design application improves design checking by utilizing a template. During the checking process, the design application divides the design layout into regions. To further improve processing speed, the design application utilizes the template. The template maps the location of the regions of a design layout during a checking process. The template comprises information such as the dimensions and location of the regions in human-readable form. Because the human-readable template is computationally simple to process, the design application may locate, divide, manage, and merge the regions of the design layout more quickly.

Abstract: The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

Abstract: The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor substrate, subjecting the stress inducing layer to a first temperature anneal, and subjecting the semiconductor substrate to a second temperature anneal subsequent to the first temperature anneal, wherein the second temperature anneal is higher than the first temperature anneal.

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Abstract: An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller.

Abstract: A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.

Abstract: An electronic circuit includes storage circuitry and a speech coder coupled with the storage circuitry to have a codebook with sets of track location numbers for respective pulses, the speech coder operable to identify a group of track location numbers in the codebook substantially equally spaced from each other by a pitch lag amount, and make a selection from the group of track location numbers of a selected track location number. Other electronic circuits, processes, methods, devices and systems are disclosed and claimed.

Abstract: A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.

Abstract: An apparatus for regulating voltage for at least one differential transistor pair having a voltage follower buffer, the voltage follower section having a first voltage-temperature response, includes: (a) a differential amplifier having two input loci and an output locus, a first input locus of the two input loci receiving a reference voltage; (b) a temperature responsive unit coupled between the output locus and ground; and (c) a feedback line coupled between the temperature responsive unit and a second input locus of the two input loci. The temperature responsive unit has a second voltage-temperature response similar to the first voltage-temperature response.