Abstract: A material-discerning device is arranged to include an antenna, a proximity sensor, a band pass filter and a processor. The antenna radiates a radio-frequency signal and a material object is located in the field created by the antenna and near the proximity sensor. Change in the amplitude of the radio-frequency signal due to the presence of the material object is detected by the proximity sensor. The change in amplitude of the radio-frequency signal is stored. The frequency of the radio-frequency signal is changed and the process is repeated until a range of frequencies have been swept and stored. After the range of frequencies has been swept and stored, the processor determines the type of material of the material object using the results of the changes in amplitude of the radio-frequency signals.

Abstract: Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input bias capacitance and a switching circuit to selectively place an input transistor in a negative feedback configuration in a first mode to charge the input bias capacitance to a calibration voltage for compensating integrator amplifier bias circuitry, with the switching circuit connecting an input node and the input bias capacitance in a second mode to integrate the input current signal across a feedback capacitance to provide a single-ended output voltage with the input bias capacitance maintaining a zero voltage at the input node.

Abstract: An integrated circuit and method are provided for accurately measuring the temperature of a die of the integrated circuit. Pairs of diodes are driven with different currents in order to generate a series of thermal voltages. The ADC measures the series of thermal voltages against an external reference voltage. Based on these thermal voltage measurements, the ADC calculates the die temperature. The different currents used to generate the series of thermal voltages are selected at specific ratios to each other in order to promote the ability of the ability of the ADC to calculate the die temperature using standard components and logic of an ADC. These thermal voltages are generated and measured using integrated components of the die for which a temperature measurement is being provided, thus reducing several sources of inaccuracies in conventional die temperature measurement techniques. Addition embodiments are provided for detecting defective diodes based on comparisons of the thermal voltage outputs.

Abstract: A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a first resistor and a second resistor, and a second path with series connection of a second bipolar transistor and a third resistor. The first and second paths are supplied current via a common node through a fourth resistor controlled by an amplifier sensing voltage drops within the first and second paths. A curvature compensation stage compensates for a variation of base emitter voltage of the bipolar transistors by drawing a compensation current from the common resistor node.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding surrounding the dielectric core member that has a second dielectric constant value that is lower than the first dielectric constant. An RJ45 compatible connector is attached to a mating end of the DWG. The RJ45 connector is configured to retain a complimentary coupling mechanism on a mating end of a second DWG.

Abstract: A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to use said methods for secured or unsecured communications with each other. Contended access is available during a random access phase. The node uses an alternate doubling of a backoff counter to reduce interference and resolve collisions with other nodes attempting to communicate with the hub in the random access phase. Non-contended access is also available, and the hub may schedule reoccurring or one-time allocation intervals for the node. The hub and the node may also establish polled and posted allocation intervals on an as needed basis. The node manages power usage by being at active mode at times during the beacon period when the node is expected to transmit or receive frames.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.

Abstract: This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and reduces CPU intervention using virtual alignment, sub-tile optimization, transaction breakdown strategy, 4D indexing, a dedicated interface with the host and frame padding. The VDMA has separate buffers for non-determinative synchronous data transfers and determinative asynchronous data transfers.

Abstract: A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while the programming switches on-state resistance impact and its VC and TC effect are minimized. The programming switch area size is greatly reduced as compared to conventional systems.

Abstract: Flyback converters are disclosed herein. An embodiment of a flyback converter includes a transformer having a primary side and a secondary side. A switch is connected to the primary side of the transformer, wherein the switch controls the current in the primary side of the transformer. A resistance is connected between the switch and a common node. The converter also includes a comparator having a first input and a second, the first input being connected between the switch and the resistor. Driver logic controls the state of the switch, wherein the output of the comparator is coupled to the driver logic. A voltage source is connected to the second input of the comparator. An error amplifier compares the voltage at the second input of the comparator to an adjustment voltage, the output of the error amplifier is coupled to the driver logic.

Abstract: Embodiments of the invention provide coexistence among independent networks through active superframe interleaving. Network hubs and devices exchange signals over a selected channel only during active superframes of their network. Network hubs broadcast coexistence information during their active superframes. A hub of network B desiring to use the selected channel first attempts to fit its active superframes within network A's inactive superframes, if available. If network A is not providing inactive superframes, then the network B hub determines whether network A is willing to coexist using active superframe interleaving on the channel. If so, the network B hub sends an interleave request message to the network A hub, which may accept the message and send back an interleave response message. The network A hub then offers new inactive superframes, and the network B hub adapts the transmissions and receptions of network B to fit within these inactive superframes.

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na?1 multiplied with the second operand bits 0 to nb?2, selectively inverting the single bit products of the signed second operand bits 0 to na?2 multiplied with the signed second operand bit nb?1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.

Abstract: A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector.

Abstract: A video system includes an encoder for generating a compressed bit stream in response to a received video signal. The encoder includes a mode decision processor that is arranged to determine whether the mode of a first pixel block in a first row is an “intra-mode” or an “inter-mode.” The encoder also includes a mode estimation processor that is arranged to estimate the mode of a left pixel block in a second row that is received after the first row in response to the determined mode of the first pixel block in the first row. The encoder also includes a pixel block processor that is arranged to process a pixel block in the second row that is to the right of the left pixel block in response to the estimated mode of the left pixel block.

Abstract: This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

Abstract: Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless scanning so as to receive wireless signals from one or more access points from among a plurality of access points positioned at plurality of locations, respectively at one or more floors from among a plurality of floors within the multi-floor environment. A first set of RSSI measurements is computed corresponding to the wireless signals. Absolute floor location information is determined based on the first set of RSSI measurements and a pre-defined objective function. The pre-defined objective function is configured to maximize a probability of a user being located at a floor so as to receive the wireless signals. A user floor location is determined based on the absolute floor location information. The user location is estimated at least in part based on the user floor location.

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively.