Abstract: A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.

Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one embodiment, the integrated circuit includes: (1) an input/output port configured to provide an external interface lead for the integrated circuit, (2) a phase locked loop having a voltage tune line coupled to a voltage controlled oscillator and (3) a voltage tune probe having a first switch coupled to a second switch and a capacitor coupled therebetween. The first switch is coupled to the voltage tune line and the second switch is coupled to the input/output port. The switches provide a bidirectional connection between the external interface lead and the voltage tune line.

Abstract: The invention provides a method and apparatus for evaluating the product quality and performances of micromirror array devices through measurements of the electromechanical responses of the individual micromirrors to the driving forces of electric fields. The electromechanical responses of the micromirrors according to the present invention are described in terms of the rotational angles associated with the operational states, such as the ON and OFF state angles of the ON and OFF state when the micromirror array device is operated in the binary-state mode, and the response speed (i.e. the time interval required for a micromirror device to transit form one state to another) of the individual micromirrors to the driving fields.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from a support structure that is operable to at least partially support the micromirror. The support structure includes at least one layer overlying at least two discrete planes that are both substantially parallel to the outer surface of the micromirror. In one particular embodiment, the support structure includes annular-shaped sidewalls that encapsulate a photoresist plug.

Abstract: A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

Abstract: Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is moved relative to the chip contact pad, thereby pulling a first length of the wire out of the wire bonding machine. Part of the wire passes through a space between a first outer edge of a first bearing race and a second outer edge of a second bearing race during the pulling of the first length. The wire is bonded on a lead. A first piezoelectric element is energized in the bond head, thereby causing it to expand and press against the first bearing race, which brakes the first bearing race and brakes the wire between the first and second races. The bond head is moved relative to the lead during the braking and severs the wire proximate to the lead.

Abstract: A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element is increased as the potential of the selected power storage device is increased when a power storage device is selected from a plurality of power storage devices that are connected in series. A certain drive voltage for turning on p-type MOS transistors Q3, Q4 of selection circuit 121 is generated based on a certain drive current Ion flowing from one power storage element to ground level GND. In other words, even if the power storage device selected by selection circuit 121 has a high potential with respect to ground level GND, the drive voltage applied between the gate and source of MOS transistors Q3, Q4 can be held substantially constant.

Abstract: A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.

Abstract: A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326.

Abstract: A control module for use in an image display system includes a gain module operable to amplify a signal received by the control module and to communicate an amplified signal having at least one clipped pixel. The at least one clipped pixel is capable of generating a color having a hue that is substantially different than a hue of a color that was specified by the signal. The control module further includes a formatter coupled to the gain module. The formatter operable to receive the amplified signal and to adjust the hue of the color associated with the at least one clipped pixel. In one particular embodiment, the hue of the color associated with the at least one clipped pixel is adjusted to substantially the hue of the color that was specified by the signal.

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: A system and method of data communication uses variable transmit antenna delays based on communication signal uplink measurements. The signals for each channel are delayed at baseband, so different delays can be used for each channel. The delay between each antenna are preferably chosen so that the strongest paths do not overlap in order to implement full transmit antenna diversity. Where it is not possible to eliminate overlapping paths, the transmitted signals are recharacterized by phase shifts and/or amplitude scaling to derive signals that inherently possess the desired communication signal characteristics.

Abstract: A novel apparatus for and a method of data transmission whereby an input data stream is distributed over a plurality of physical channels within a logical channel group. Transmission of data over the channel group appears as transmission over a single logical channel having a bandwidth approximately equal to the sum of the physical channel bandwidths. The physical channels making up the logical channel group may have different bandwidth capacities. The invention comprises a method of data unit distribution among a plurality of physical channels including the consideration of the bandwidth capacities of the individual physical channels in implementing the distribution algorithm, and the capability of reproducing the order of the transmission of the data units on the receiving side without the need for additional fields or modification of existing fields of the data units.

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.