Abstract: A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a first change matrix associated with a portion of the first sample set of data; a first memory component that stores the first change matrix; a second capturing component that captures a second sample set of data; a second generating component that generates a second change matrix associated with a portion of the second sample set of data; a second memory component that stores the second change matrix; a third capturing component that captures a third sample set of data; a third generating component that generates a third change matrix associated with a portion of the third sample set of data; a comparing component that compares the third change matrix with the first change matrix to obtain a first comparison, and compares the third change matrix with the second change matrix to obtain a second comparison; and an adapting component that adapts the digi

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: Microphone signals are received from a microphone. The microphone signals represent first sound waves. A determination is made about a type of noise that likely exists in the first sound waves. In response to the type of noise, cancellation signals are generated by filtering the microphone signals with at least one of: a first filter in response to the type of noise indicating that a first type of noise likely exists in the first sound waves; and a second filter in response to the type of noise indicating that a second type of noise likely exists in the first sound waves. In response to the cancellation signals, second sound waves are output from a speaker for cancelling at least some noise in the first sound waves.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams.

Abstract: An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

Abstract: An interleaved forward voltage converter having a first inverter stage has a first transformer having a first secondary winding coupled to a filter inductor. A second converter stage has a second transformer having a second secondary winding coupled to the filter inductor. A diode is coupled between the first and second secondary windings to automatically connect the first and second secondary windings in series when a duty cycle of the converter exceeds 50%. An interleaved forward voltage converter can connect the two primary windings in either parallel or a series configuration. The two secondary windings can be connected in either parallel or a series configuration. Having the two primary windings in parallel and the two secondary windings in series allows the converter to operate with a lower input voltage. Having the two primary windings in series and the two secondary windings in a parallel configuration allows the converter to operate with a higher input voltage.

Abstract: A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.

Abstract: Circuits and methods for detecting the presence of a leading-edge phase-cut dimmer. The dimmer detector comprises an edge detector, a pulse stretcher and a filter. The edge detector detects whether an input signal has a rapidly rising edge and generates an output signal pulse if a rapidly rising edge is detected. If the edge detector outputs a signal pulse, the pulse stretcher generates a stretched pulse having a duration that is longer than the signal pulse received from the edge detector. The filter produces a dimmer detect signal that indicates whether a leading-edge phase-cut dimmer is detected. If the pulse stretcher output signal comprises at least a predetermined number of stretched pulses within a predetermined amount of time, the dimmer signal signals the presence of a leading-edge phase-cut dimmer.

Abstract: A DC-DC converter includes a first differential voltage sensor to detect a first inductor current by sensing a first differential voltage across a first power stage of the DC-DC converter. A second differential voltage sensor detects a second inductor current by sensing a second differential voltage across a second power stage of the DC-DC converter. An integrator stage combines the first differential voltage from the first power stage and the second differential voltage from the second power stage to generate a compensation signal to adjust current balancing for the DC-DC converter.

Abstract: A method and an encoder for SSIM-based bits allocation. The encoder includes a memory and a processor utilized for allocating bits based on SSIM, wherein the processor estimates the model parameter of SSIM-based distortion model for the current picture and determines allocates bits based on the SSIM estimation.

Abstract: A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals, blanks the current sense signals in a first converter channel for periods of time that correspond with the actions of the transistors in a second converter channel, where the actions result in noise spikes across the converter that falsely interfere with current sensing in the first converter channel.

Abstract: Checksum computation for video coding is provided that breaks the dependency between the color components of a picture in the prior art. More specifically, rather than computing a single checksum for a picture as in the prior art, a separate checksum is computed for each color component. Computing a separate checksum for each color component enables parallel computation of the component checksums. Methods are provided for computing three separate checksums after a picture is decoded. Methods are also provided for computing three separate checksums on a largest coding unit basis, thus allowing the checksums for a picture to be computed as the picture is being decoded.

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract: Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q2) having a collector terminal coupled to an emitter terminal of the first transistor (Q1); a third transistor (Q3) having an emitter terminal coupled to an emitter terminal of the second transistor (Q2) and to a ground node, a collector terminal coupled to a current source (Ibias), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q2); and a capacitor (C1) coupled to the base terminals of the second and third transistors (Q2 and Q3) and to a second input node (vinn), wherein the first and second input nodes (vinp and vinn) are differential inputs.

Abstract: The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Abstract: Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.