Abstract: A method for determining whether a tire is in rotation is provided. A measured acceleration is compared to a first threshold after a first timer indicates that a first period has lapsed, and indication that the tire is in rotation is provided if at least one of the measured accelerations is greater than the first threshold. If an absolute difference between consecutive measured accelerations is greater than a second threshold, an indication that the tire is in rotation is also provided. Additionally, the second timer is started if the absolute difference is greater than the second threshold and if a second timer is not running, and indication that the tire is rotating is provided if the absolute difference is less than a predetermined threshold and if the second timer is running.

Abstract: An imaging apparatus is provided. The apparatus generally comprises an array and storage elements. The array includes photosensitive cells that are arranged in a plurality of columns and a plurality of rows such that each column includes a set of photosensitive cell pairs that have a shared region with a share floating diffusion region and a shared selection transistor. Also, the location of each shared region of each column is shifted by one row in each adjacent column.

Abstract: Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of the wafer. The resist mitigates the creation of contaminants, such as nitride flakes, for example, that can develop when an oxide, nitride, oxide (ONO) layer is removed from the back or in-active side of the wafer. In the absence of the resist, such flakes may migrate to the front or active side of the wafer and cause defects to form therein, which can result in yield loss.

Abstract: System and method for preprocessing a signal for transmission by a power amplifier. In a preferred embodiment a multiple input multiple output processor is coupled to a plurality of power amplifiers for transmitting a signal, where the number of power amplifiers exceeds the number of antennas. The multiple input multiple output processor performs an algorithm to optimize the output vector ensuring that the transmit power for any one amplifier is below a predetermined threshold. In a preferred embodiment a Remez optimization algorithm is performed. Alternative optimization algorithms may be used. In a preferred embodiment the processor is a single integrated circuit. A method is disclosed where a multiple output vector is produced for transmission, using an optimization algorithm to produce an output vector that ensures that for any of the power amplifiers, the transmit power is maintained below a predetermined threshold.

Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

Abstract: Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.

Abstract: A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to generate a branch packet comprising branch bits. At least some of the branch bits are associated with branch instructions executed by the processor. The trace logic flushes invalid branch bits in the branch packet with a common bit, the common bit an inverse of a valid branch bit. The trace logic outputs the branch packet with an indicator comprising the valid branch bit.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations.

Abstract: An integrated programmable device has a plurality of signal inputs (P1, P2, P3) connected to respective ones of a plurality of switching elements (S1, S2, S3). Each switching element (S1, S2, S3) has an associated enable line (E1, E2, E3). A control circuit (15) activates one or more selected signal inputs (P1-P3) in accordance with a channel select signal (16) via these enable lines (E1, E2, E3). Feedback lines (F1, F2, F3) are connected to corresponding enable lines (E1, E2, E3) to a channel feedback indicative of which signal inputs (P1, P2, P3) is enabled. This allows determination whether the enabled signal inputs (P1, P2, P3) correspond to the channel select signal (16) and initiates an exception handling in case of a mismatch. The comparison can be performed by a compare logic circuit (40) or the channel feedback can be stored in a memory (30) accessible by a software program (60), which performs the comparison.

Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

Abstract: A method and apparatus for scheduling in a wafer fab. The method comprising means for weighting inventories according to at least one of logpoints or reticle, and photolithography units, means for scheduling one of said inventories on one of said photolithography units, wherein said one of said inventories has a maximal weighting and means for eliminating any of said inventories not scheduled according to constraints.

Abstract: A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels with the requirement they be re-ordered at the receiving side. The mechanism is particularly suitable for use in cable systems adapted to implement the DOCSIS 3.0 specification which permits the bonding of a plurality of downstream channels into a single virtual high data rate pipe. In operation, received packets are stored in a memory whereby a pointer to the memory storage location is written into a context table diagram in accordance with the sequence number extracted from the packet. Packets are released in sequence order regardless of the order in which they were received.

Abstract: A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere (105) is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate (110) with a chip attachment location and a third set of contact pads (112) near the location. Low profile bond wires (130) span between the pads of the third set and the second set. A second semiconductor chip (140) of a size has a fourth set of contact pads (141) at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

Abstract: A computational algorithm provides new and effective interference cancellation of the in-band spurious signals for the Orthogonal Frequency Division Multiplex (OFDM) transmitters. This new interference cancellation transmits non-zero tones may be used to cancel the interference generated by the modulated data signals. This minimizes the number of tones used and maximizes the interference suppression achieved at the same time. The technique described is one of active interference cancellation (AIC).

Abstract: A system for, and method of, entropy coding. In one embodiment, the system includes: (1) a memory configured to contained initialized accumulated statistics coding variable values and (2) a processor configured to employ the initialized accumulated statistics coding variable values to context-adaptive encode multiple symbols until an accumulated statistics update condition occurs and updating and store the accumulated statistics coding variable values in the memory only upon occurrence of the accumulated statistics update condition.