Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Abstract: A DCDC converter includes a controller, an up/down counter, a first power stage and a second power stage. The controller generates an up/down control signal. The up/down counter generates a first power stage control signal and a second power stage control signal based on the up/down control signal. The first power stage generates a first output current at a first phase and at a first voltage based on the first power stage control signal. The second power stage generates a second output current at a second phase based on the second power stage control signal. The up/down counter modifies the first power stage control signal to control the first power stage such that the first output current attenuates from a first power stage output to a secondary first power stage output. The controller can further output a control signal to modify the first voltage of the first power stage.

Abstract: Embodiments of the invention provide methods for user equipments to implicitly determine the location for the transmission of uplink control signaling information, that is in response to downlink data packet transmissions, using information that is already available through the downlink control signaling for the respective downlink scheduling assignments. No additional explicit downlink control signaling is required for the transmission of the above uplink control signaling from each user equipment.

Abstract: A method and apparatus for coordinating a multi-point wireless transmission between a plurality of geographically separated transmission points and at least one user equipment.

Abstract: An instruction cache includes instruction storage, a plurality of lock indicators, and control logic. The instruction storage includes a plurality of cache blocks to store instructions. Each of the lock indicators is associated with one of the cache blocks so as to control access to the associated cache block. The control logic is configured to: set to a write disable state, on access of a given one of the cache blocks, a given one of the lock indictors associated with the given one of the cache blocks; to determine whether a given instruction is stored in the instruction storage; and to deny write access to the given one of the cache blocks that is assigned to store the given instruction based on the given one of the block indicators being set to the write disable state.

Abstract: A duty-cycled acoustic sensor saves power, for example, by operating for relatively short periods of time in a repetitive manner. A sensor bias current provides operating power to the sensor. An output analog signal from the sensor carries the information induced by the sensor upon the bias signal. Capacitive coupling is employed to remove direct DC voltage from the output analog signal to generate an analog input signal for acoustic analysis. A capacitor for capacitive coupling is pre-charged to reduce the charging time of the capacitor as the sensor is being powered up. After the capacitor is sufficiently precharged, acoustic analysis is performed on the analog input signal. The sensor is powered down by substantially blocking current flow through the sensor, which saves power. Results of the acoustic analysis can be used, for example, to control parameters of the duty-cycling of the acoustic sensor.

Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.

Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract: A method, apparatus and system for a video encoder for selecting a block of intermediate size from a set of block sizes for intra-prediction estimation for encoding a video signal. A set of neighboring blocks with the intermediate size are tested for combining. If the set of neighboring blocks are determined to be combinable, the video encoder selects a larger block size formed by the tested neighboring blocks for encoding. On the other hand, if the set of neighboring blocks are determined to be not combinable, the video encoder selects a smaller block size from the set of tested neighboring blocks for prediction. Furthermore, intra-prediction is determined by first intra-predicting a block with intermediate modes in a set of modes. Then the intra-predictions are performed for the neighboring modes of at least one intermediate mode.

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA includes a USB accessory port. The ACA bridge circuit includes detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller.

Abstract: A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier includes a boost circuit configurable to increase a transconductance of the droop amplifier during an upward transition of the reference voltage. The switching regulator further includes a comparator responsive to the droop voltage and a current sense signal. The comparator is configured to initiate switching in the switching regulator.

Abstract: A data reception circuit removes reliance on stacked transistors providing analog logic processing. A first trigger element outputs an up signal in response to receiving an indication of receipt of a data signal by a receiving device without consideration of an output signal from the receiving device. A second trigger element outputs a down signal in response to receiving an indication of receipt of a data signal by a receiving device without consideration of an output signal from the receiving device. Switches control provision of signals to a received signal line for the receiving device in response to the outputs of the trigger elements. A blocking feedback circuit provides a blocking signal for the receiving device to effect blocking the receiving device from sending data to the sending device when the receiving device is receiving data from the sending device.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface of a spatial light modular to an image field using a projection system; capturing light from the image field using the projection system, the projection system directing at least a portion of the captured light to the spatial light modulator; and directing at least a portion of the received captured light to an image capture system using the spatial light modulator.

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

Abstract: Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an allocation from the eNodeB comprising a plurality of periodic transmission instances for a channel quality indicator (CQI) and a schedule comprising a plurality of periodic transmission instances for a rank indicator (RI), wherein the CQI comprises RI and other CQI fields. The UE then transmits an RI without transmitting the other CQI fields in a transmission instance allocated for both RI and other CQI fields.