Abstract: This invention is a method of wireless communication having a communications protocol providing more downlink subframes than uplink subframes. The user equipment transmits a combination of a plurality of ACK/NAK response signals and related data. The related data could be the number of bits N of the plurality of ACK/NAK response signals or the number of detected downlink communications grants S requiring ACK/NAK response signals. This related data could be a cyclical redundancy check set of bits which may be scrambled upon the numbers N or S. Similar selections are feasible with resource elements or an index of a modulation symbol or codeword.
Abstract: An active-passive continuous-time analog-to-digital converter and a method of continuous-time sigma-delta analog-to-digital conversion. In certain embodiments, the converter has a reduced power consumption, and the method requires less power to carry out. One embodiment of the converter has a signal input and includes: (1) an input summing junction coupled to the signal input, (2) a folded cascode transconductor having an input coupled to the input summing junction and (3) a feedforward path that couples the signal input to at least two nodes within the folded cascode transconductor.
Abstract: The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially(SPER) (110). The non-amorphizing tail implant is generally annealed (106) before a doped amorphous layer for SPE is formed (107). SPE provides a high active dopant concentration in a shallow layer. The non-amorphizing tail implant (105) expands the source/drain extension region beyond the range dictated by the SPE-formed layer and keeps the depletion region of the P-N junction away from where end-of-range defects form during the SPE process. Thus, the SPE-formed layer primarily determines the conductivity of the junction while the tail implant determines the location of the depletion region. End-of-range defects form, but are not in a position to cause significant reverse bias leakage.
Abstract: A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions (224).
Type:
Application
Filed:
May 7, 2009
Publication date:
September 10, 2009
Applicant:
Texas Instruments Incorporated
Inventors:
PR Chidambaram, Haowen Bu, Rajesh Khamankar, Douglas T. Grider
Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.
Abstract: A system for providing a desired substantially constant resistance includes a first transistor interconnected between a first node and a second node. The system also includes a second transistor, the second transistor being diode connected, the first transistor and the second transistor forming a current mirror. A voltage divider is coupled to provide a portion of a voltage associated with the first transistor to the second transistor, the voltage divider being configured parallel to the first transistor to provide a substantially constant resistance between the first node and the second node. A current source is coupled to the second transistor, the current source being controlled to draw an amount of current through the second transistor to set the substantially constant resistance substantially equal to the desired substantially constant resistance.
Abstract: An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
Abstract: A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first analyzing the network from call signaling and message standpoints, leading to the identification of suitable surveillance access points (SAPs) for packet interception. A Delivery Function (DF) facilitated by the network service provider provides the means to intercept (without alteration) and replicate packets transmitted across the SAPs. The packets are then transmitted via the DF for collection within a Collection Function (CF), which is managed by a Law Enforcement Agency (LEA), for analysis by the LEA. This analysis provides, among other benefits, the opportunity to decrypt the intercepted packets and to identify additional suitable SAPs. In demonstrating the procedure, several embodiments of network surveillance models are described. Each one identifies the location of SAPs for that model.
Type:
Grant
Filed:
February 10, 2005
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Shwu-Yan Chang Scoggins, Debbie E. Greenstreet
Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell.
Abstract: A mirror device and a method for audio feedback of a MEMS mirror device are presented. The mirror device includes a mirror with a reflective surface located to intercept a modulated beam of light produced by a laser. The mirror oscillates on a hinge axis structure A microphone detects the mirror oscillation information. The mirror device further includes a mirror driver system and a video controller system. The mirror driver system causes the mirror to rotate about the hinge axis structure. The video controller system uses the information received from the microphone, and the information received from the mirror-driver controller, to control the output of the laser.
Abstract: A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert the buffer “Full” flag. In turn, the full flag is used by the instruction fetch logic as an indication of when to stop fetching further instructions.
Abstract: Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to whether the Java WIDE opcode is to be used as a prefix, and when the Java WIDE opcode is not to be used as a prefix, a task assigned to the Java WIDE opcode is performed.
Abstract: Inter-integrated circuit-capable devices for use on an inter-integrated circuit bus are disclosed. The inter-integrated circuit-capable devices include integrated, internally-configurable addressing registers in place of external pins. Cascaded systems of inter-integrated circuit-capable devices for easier addressing are also disclosed as are methods for writing address identifier codes to addressing registers of the cascaded, inter-integrated circuit-capable devices.
Abstract: Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver. The radio frequency energy receiver is operable to receive a radio frequency energy and to convert the radio frequency energy to a DC current. In addition, the device further includes a first clock generator that generates a first clock at a first frequency and second clock generator that generates another clock based on the first clock. The first clock generator includes a duty cycle correction circuit. The second clock has a positive going clock edge for each edge of the first clock.
Type:
Grant
Filed:
May 8, 2006
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Ganesh K. Balachandran, Raymond E. Barnett
Abstract: The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test systems are configured to test the semiconductor devices using overlapping test setups by configuring various test system elements. The various test system elements are programmed and prepared for subsequent tests concurrently with tests executing on the semiconductor devices. The test results are computed by various software computation modules configured to independently execute in parallel with the subsequent tests. The resultant test data of an executed test is shared among the various concurrently executing software computation modules using shared information storage. A tester user interface, executing on test system, provides an interface between user test scripts and software computation modules.
Type:
Grant
Filed:
July 8, 2003
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Dennis Harold Burke, Jr., Mark Allen Erickson, Kevin Dale Bittick
Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).
Type:
Grant
Filed:
April 27, 2007
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Shaofeng Yu, Freidoon Mehrad, Jiong-Ping Lu
Abstract: A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
Type:
Grant
Filed:
November 8, 2006
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Marc E. Royer, Bharath M. Siravara, Steven C. Bartling, Charles M. Branch, Pedro R. Galabert, Neeraj Mogotra, Samil D. Kamath
Abstract: A novel and useful load compensation circuit and associated pre-power amplifier constructed therefrom. The load compensation circuit functions to maintain a nearly constant output impedance of the pre-power amplifier by use of a switch matrix comprising a plurality of transistors. The switch matrix is placed in parallel with the output of the pre-power amplifier (PPA). Transistors are turned on or off within the load compensation switch matrix so as to maintain a nearly constant output impedance of the PPA throughout the entire modulation range. At maximum PPA output power, all transistors in the load compensation switch matrix are turned off thereby minimizing the extra output loading and reducing the overall power output. As output power decreases, additional numbers of transistors in the load compensation switch matrix are turned on so as to maintain a constant output impedance of the PPA.
Abstract: A CMOS integrated circuit (12) for correction of the duty cycle of a clock signal has a correction amplifier (16) to which a clock signal (14) is applied. The output of correction amplifier (16) is connected to an output buffer (18) and to an input of a duty cycle detector (20), the output of which is fed back to a control input (VC) of correction amplifier (16), thus forming a control loop. The duty cycle detector (20) comprises a buffer amplifier (22), an RC low pass circuit and a second inverter (24). A deviation of the duty cycle of the clock signal is detected in the duty cycle detector 20 and used to correct the duty cycle in the correction amplifier 16.