Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1?xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.

Abstract: A fixture for securing at least one test printed circuit board assembly (PCBA) including a PCB having semiconductor devices mounted thereon during vibration or mechanical shock testing. A top plate includes top features including a continuous top outer ring, at least one inner top aperture within the top outer ring, and a plurality of outer top apertures positioned beyond the top outer ring including a top probe access aperture and a threaded aperture. A bottom plate includes bottom features including a bottom continuous outer ring, at least one inner bottom aperture, and plurality of outer bottom apertures including a bottom probe access aperture and table mounting aperture. The threaded apertures accept a fastener that clamps the top plate to the bottom plate for the outer rings to secure a full periphery of the PCB between the top plate and bottom plate.

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Abstract: An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract: An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.

Abstract: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

Abstract: A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips.

Abstract: A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.

Abstract: Gang clips (500) having a flat area (510), a ridge (510a), and tie bars (530b) extending from the flat area, the end portions of the ties bars aligned in a common x-direction; a plurality of gang clips having respective end portions of tie bars merged in x-direction to form an elongated chain (701) of clips; and a plurality of chains arrayed parallel to each other, free of tie bars between adjacent chains, the plurality having the chain ends tied at both ends (730a) to rails (740) normal to the chains to form a matrix (700) of clips having the rails as a stable frame.

Abstract: Electric Vehicle Service Equipment (EVSE) and Electric Vehicle (EV) are disclosed n. In an example embodiment, a modem is coupled to the pilot wire that couples the EVSE and the EV. The modem transmits both pulse width modulation (PWM) command signals and power line communication (PLC) signals to a remote device via the pilot wire. The modem interleaves the PWM and PLC signals on the pilot wire so that latency requirements for the PWM signals are maintained. The modem supports parallel protocol stacks in which PLC signals are processed in a first path and PWM signals are processed in a second path that bypasses the first path and provides the PWM signals directly to a MAC layer. The modem may create a modified frame for the PLC signals to maintain the latency requirements.

Abstract: User equipment (UE)-initiated accesses within a cellular network are optimized to account for cell size and to reduce signaling overhead. A fixed set of preamble parameter configurations for use across a complete range of cell sizes within the cellular network is established and stored within each UE. A UE located in a given cell receives a configuration number transmitted from a nodeB serving the cell, the configuration number being indicative of a size of the cell. The UE selects a preamble parameter configuration from the fixed set of preamble parameter configurations in response to the received configuration number and then transmits a preamble from the UE to the nodeB using the preamble parameter configuration indicated by the configuration number.

Abstract: Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract: A first depth map is generated in response to a stereoscopic image from a camera. The first depth map includes first pixels having valid depths and second pixels having invalid depths. In response to the first depth map, a second depth map is generated for replacing at least some of the second pixels with respective third pixels having valid depths. For generating the second depth map, a particular one of the third pixels is generated for replacing a particular one of the second pixels. For generating the particular third pixel, respective weight(s) is/are assigned to a selected one or more of the first pixels in response to value similarity and spatial proximity between the selected first pixel(s) and the particular second pixel. The particular third pixel is computed in response to the selected first pixel(s) and the weight(s).

Abstract: Methods, electronic devices and USB charger apparatus are presented for fast USB charging, in which a high voltage master of the device detects a connected high voltage charger and selectively connects a current circuit to source or sink a current to or from one USB cable data signal conductor while providing a non-zero voltage to the other USB cable data signal conductor to configure the charger apparatus to provide charging power at a particular high voltage level above a nominal voltage level.

Abstract: A disk drive preamplifier integrated circuit. The integrated circuit comprises a differential output driver configured to drive readback data to an output load, wherein the output driver comprises a differential mode filter configured to filter alternating current of an on-chip power supply.

Abstract: A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.

Abstract: An apparatus having an X-ray sensor assembly with X-ray blocking pixels divided by X-ray transmitting gaps with the X-ray blocking pixels casting an X-ray blocking shadow; and a die containing signal processing electronics, with the signal processing electronics positioned substantially entirely within the X-ray blocking shadow. A method for detecting the alignment between the X-ray sensor assembly and the die is disclosed. Also disclosed is an X-ray computed tomography machine having a printed circuit board (“PCB”), a die embedded in the PCB, and a signal source wherein signals are routed to and from the die by traces on at least one of the surfaces of the PCB.

Abstract: A system comprising a processor and a compression module coupled to the processor. The compression module is adapted to perform motion estimation on video data using an algorithm, the motion estimation performed at a rate. If the processor determines a difference between the rate and a target rate, the processor adjusts a precision level of the algorithm such that the difference is decreased.

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.