Abstract: In a burn-in test configuration wherein a chip board having a plurality of semiconductor chips engages a heat sink board having a plurality of heat sinks. When the boards are operationally engaged, each semiconductor chip has a heat sink spring-loaded against the semiconductor chip. Posts coupled to one board engage posts located on the other board. The engagement of the posts orients and secures the relative positions of the two boards. A clip is provided that secures the relative position of the two boards when the two sets of posts are engaged. To uncouple the two boards, a pressure on the side of the clip permits the two boards to separate.

Abstract: A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.

Abstract: Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a negative charge to a memory array bitline through a zero cancellation capacitor while a memory cell plateline signal is applied during a read operation, wherein one or more layers of the zero cancellation system layout is identical or substantially identical to that of the memory cells of the array.

Abstract: A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably the negative impedance cell has a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage has a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.

Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

Abstract: A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.

Abstract: Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off.

Abstract: Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the generation of simultaneous actions across units operating in series, with both the data recording and user command execution happening at the same point in the trace data stream.

Abstract: A method (300) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask (310) having a plurality of symmetric and asymmetric test structures thereon, and image processing one or more semiconductor wafers (320) using the fabricated mask to create a plurality of symmetric and asymmetric resist structures overlying the one or more wafers. At least one critical dimension of the symmetric resist structures and the asymmetric resist structures are measured (330), thereby generating symmetric and asymmetric critical dimension data, and a difference between a desired feature size of the symmetric and asymmetric structures and the measured feature size of the symmetric and asymmetric structures is evaluated (380) in order to generate an optical proximity correction model (398) based thereon.

Abstract: In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].

Abstract: A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106).

Abstract: A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor.

Abstract: The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple data sources, including building one or more single-source data words by iteratively selecting a data source, writing data from the data source to each data section within a single-source data word if enough data is available to fill the single-source data word, copying a data bit of the single-source data word to a data bit within a start word, and clearing the data bit of the single-source data word; and including transmitting the one or more single-source data words after transmitting both a start word and one or more multi-source data words within the same data frame The data written into the one or more single-source data words and the data most recently written into the one or more multi-source data words originate from the same data source.

Abstract: This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.

Abstract: Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.

Abstract: Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a second conductivity type between a channel (78) of a first conductivity type and a drain (74) to inhibit channel hot carrier or direct tunneling degradation of the transistor gate dielectric (64) for high voltage operation. The voltage drop region (80) has more dopants of the first conductivity type and/or fewer dopants of the second conductivity type than does the well (82) so as to shift the high fields away from the transistor gate dielectric (64).

Abstract: A method and system for downloading firmware by a device controller from a data source while connected to a host. The device controller connects to the host and waits for a signal or communication from the host. The device controller responds to the signal or communication with a negative acknowledgement (NAK), and downloads data for a predetermined period of time based on the request signal or communication type received from the host. The device may use a pointer to track the progress of the download. Once the device has completed the download, the device responds normally to the host.

Abstract: The invention provides methods and apparatus for drying the backside of semiconductor wafers in a spin-coating environment. Solvent is evaporatively dried from a semiconductor wafer held in a spin mechanism. The undried wafer is sprayed with one or more jets of pressurized gas from gas ports disposed about the spin mechanism.

Abstract: Embodiments of the present disclosure provide a memory element, a method of constructing a memory element, a method of operating a memory cell, an SRAM cell and an integrated circuit. In one embodiment, the memory element includes a pair of cross-connected CMOS inverters having first and second storage nodes. Additionally, the memory element also includes a capacitive component connected between the first and second storage nodes and configured to provide a supplemental capacitance to extend a read signal for sensing a memory state of the inverters.

Abstract: Embodiments of the present disclosure provide an integrated circuit including a functional memory and methods of characterizing a component or a defect of a memory cell in the functional memory. In one embodiment, the functional memory includes row and column periphery units having periphery sourcing and sinking voltage supply ports, an array of memory cells organized in rows and columns and a word line controlled by a word line driver that provides row access to a memory cell of the array. Additionally, the functional memory also includes a bit line controlled by a direct bit line access circuit that provides direct bit line access to the memory cell through a bit line analog access port and an independent voltage supply port.