Abstract: The motion-compensated temporal interpolation using an optical flow defined in an interpolation frame from a subsequent frame, and interpolating from either the prior or the subsequent frame depending upon the divergence of the optical flow.

Abstract: The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an SDRAM, immediately after that, access to FLASH is started, and a shared bus controller outputs the write/read address with respect to FLASH on the address bus. Then, after the end of data transfer on the data bus, either the shared bus controller outputs the write data, or FLASH can output the read data on the data bus by means of a strobe signal. Then, the input of address is established by FLASH, and, as the shared bus controller asserts a strobe signal, either FLASH fetches the write data on the data bus, or the shared bus controller fetches the read data on the data bus.

Abstract: Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure.

Abstract: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.

Abstract: In an analog-to-digital converter used to convert and store in buffer registers signals from a plurality of peripheral devices, a mode is provided wherein the processing unit can directly access the buffer registers into which the conversion results have been stored.

Abstract: A low voltage amplifier having a class-AB control circuit which generates minimal or no surge current when the output of the amplifier clips to ground or the negative rail. The amplifier includes an input stage, a summing circuit, a class-AB control circuit and an output stage. The input stage connects to a first current source and couples to receive a pair of differential input signals to generate intermediate signals that are summed together using the summing circuit. A second current source supplies the summing circuit with current. The class-AB control circuit receives the summed signals from the summing circuit to provide control for the output stage which generates the amplifier result at the output of the amplifier which delivers current to drive an external load.

Abstract: In an optical image acquisition and information transmission system, the system components can be fabricated, according to a first implementation, in a stack positioned on a circuit board. According to a second implementation, the system components are fabricated on a single substrate using the same semiconductor processes for each component. Both implementations result in better performance parameters. These systems are particularly useful as control devices wherein information resulting from processing the acquired image rather than the image itself is transmitted.

Abstract: The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.

Abstract: Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

Abstract: The invention provides a method and apparatus for evaluating the quality of microelectromechanical devices having deformable and deflectable members using resonation techniques. Specifically, product quality characterized in terms of uniformity of the deformable and deflectable elements is inspected with an optical resonance mapping mechanism on a wafer-level.

Abstract: A semiconductor device for a tuner generates a local oscillation signal inside or selects a local oscillation signal introduced from the outside, and controls the power consumption of the circuit used for generating the local oscillation signal. The diversity receiver constituted using the semiconductor device has semiconductor device 1 selected to generate a local oscillation signal inside and semiconductor device 2 selected to introduce a local oscillation signal from the outside. The local oscillation signal of the semiconductor device 2 is driven by the local oscillation signal of the semiconductor device 1. Consequently, any unnecessary power consumption of the circuit generating the local oscillation signal of semiconductor device 2 can be reduced. In addition, since they are the same type of semiconductor device, the uniformity of the operating characteristics of the diversity receiver can be improved.

Abstract: A multi-mode color filter 400 having an inner hub region 402 used to mount the color filter 400 to a motor shaft. A first track 404 and a second track 406 of color filter segments are formed on the color filter, as is an optional clear track 406. The first and second tracks each have a different set of color filters. One set of filters is chosen to improve image brightness, another set is selected to improve color saturation. Typically, the set of filters used to improve brightness includes one or more clear segments, while the set of filters selected to improve color saturation does not. Depending on the image being projected, the user or the display controller moves the color wheel to select a particular filter set.

Abstract: System and method for driving an LCD using a data-dependent, logic-level drive scheme. A preferred embodiment comprises determining a desired state of each pixel in an LCD pixel segment, deriving a drive waveform based upon the state of all pixels in the LCD pixel segment, and outputting the drive waveform to the LCD pixel segment. By using the states of all the pixels in the LCD pixel segment in the determination of the drive waveform, it is possible to increase the on and off voltage to help improve display quality.

Abstract: Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.

Abstract: An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

Abstract: A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate broken die lands or other malfunctions.

Abstract: A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send via the connection, the target hardware gives priority to trace information generated by a primary processor core associated with a token over trace information generated by a secondary processor core not associated with the token. The token is associated with one of the multiple processor cores at a time.

Abstract: A spatial light modulator comprises a solid-state chiral material disposed between electrodes such that the polarization direction of the polarized light incident thereto can be controlled through an electrical field established between the electrodes.

Abstract: A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

Abstract: One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed.