Patents Assigned to Texas Instruments
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Publication number: 20090170222Abstract: A method for semiconductor processing is provided, wherein a semiconductor wafer having undergone polishing is provided. The semiconductor wafer has an active region positioned between one or more moat regions, wherein the one or more moat regions have an oxide disposed therein. A top surface of the active region is recessed from a top surface of the moat region, therein defining a step having a step height associated therewith. A step height is measured, and a photoresist is formed over the semiconductor wafer. A modeled step height is further determined, wherein the modeled step height is based on the measured step height and a desired critical dimension of the photoresist. A dosage of energy is determined for patterning the photoresist, wherein the determination of the dosage of energy is based, at least in part, on the modeled step height. The photoresist is then patterned using the determined dosage of energy.Type: ApplicationFiled: November 25, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Brian Douglas Reid, James David Bernstein, Hongyu Yue, Howie Hui Yang, Mark Boehm
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Publication number: 20090166832Abstract: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of the interposer, which has a thickness (111) equal to or smaller than the sum of the assembled two chips. Adhesive material (160) holds the tapes parallel to the interposer and the chip surfaces together. Solder balls (180) and discrete components (170) may be attached to the outside surfaces of the tapes.Type: ApplicationFiled: February 4, 2009Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Rajiv Carl Dunne
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Publication number: 20090167845Abstract: In one embodiment, a method of rendering stereoscopic images includes providing eyewear having a pair of lenses. Each lens is transitioned between an optically-shuttered state and an optically-transmissive state. The transitioning is in response to a voltage waveform applied substantially simultaneously to at least a portion of each lens. Each lens transitions between states in opposition to the other lens.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Sajjad Ali Khan
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Publication number: 20090168487Abstract: One embodiment of the present invention relates to a method for reducing the imprint of a ferroelectric memory cell. The method comprises storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising comprises either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation. Other methods and circuits are also disclosed.Type: ApplicationFiled: December 26, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: John Anthony Rodriguez, Sanjeev Aggarwal
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Publication number: 20090170240Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.Type: ApplicationFiled: March 11, 2009Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: William P. Stearns, Nozar Hassanzadeh
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Publication number: 20090166755Abstract: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.Type: ApplicationFiled: September 17, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Srinivasan Chakravarthi, Periannan Chidambaram
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Publication number: 20090168488Abstract: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: John Rodriguez
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Publication number: 20090170259Abstract: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Brian Edward Hornung, Rajesh Gupta, Mike Voisard
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Publication number: 20090168146Abstract: A stabilizer mechanism is coupled to a deformable element of a microelectromechanical device for reducing unwanted deformation of the deformable element by increasing the stiffness of the deformable element in selected other directions than the direction along which desired deformation is performed.Type: ApplicationFiled: December 27, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Larry Joseph Hornbeck
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Publication number: 20090172496Abstract: One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value. The memory address is incremented, and the inversion status data state is toggled once the address counter addresses the entire memory array. Other methods and circuits are also disclosed.Type: ApplicationFiled: September 8, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Per Torstein Roine
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Publication number: 20090169740Abstract: The objective of the invention is to prevent unwanted dripping of SOG from nozzles and coating of crystallized or solidified particles in an SOG coater that utilizes different kinds of SOG material. The SOG supply method includes a step in which, when executing processing for supplying a first spin-on glass to a lot from a first nozzle, a prescribed amount of second spin-on glass is discharged from a second nozzle at the beginning or the end of the processing of said lot. Furthermore, the SOG supply method includes a step in which the second nozzle is cleaned at the beginning of processing of the substrates contained in a lot.Type: ApplicationFiled: December 29, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Kohtaro Teshima, Hironobu Aoyagi
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Publication number: 20090167329Abstract: Methods and apparatus for open lamp detection in electronic circuits are disclosed. An example apparatus to perform open circuit detection associated with an electrical component included in a device disclosed herein comprises a sampling circuit to attempt to pull a sampling current through the electrical component during initialization of the device, a comparator to compare a result produced by the sampling circuit to a reference value, and a timing circuit to cause the sampling circuit to attempt to pull the sampling current through the electrical component and to cause an output of the comparator to be stored after the comparator has compared the result produced by the sampling circuit to the reference value.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Gilbert Seung-Zoo Lee, James Bumsik Cho, Eung-Suen Kim, Johnny Jin-Hui Lee
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Publication number: 20090170277Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.Type: ApplicationFiled: December 29, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
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Publication number: 20090166673Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Kamel Benaissa
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Publication number: 20090167442Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Stanley J. Goldman
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Publication number: 20090166675Abstract: This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.Type: ApplicationFiled: December 30, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Mahalingam Nandakumar
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Publication number: 20090171605Abstract: In one embodiment, a method includes receiving inspection data from an optical inspection tool. The inspection data represents a plurality of surface features of a substrate. The inspection data is compared to a first pattern. The first pattern corresponds to a second pattern formed by dispensing a flowing substance on a surface of the substrate. The method further includes determining, based at least in part on the comparison, if the inspection data indicates one or more defects.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Gary Thomson
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Publication number: 20090170324Abstract: In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly from the substrate. The MEMS comprises structures and corresponding landing pads. Dibs are disposed outwardly from the substrate. Each dib has a surface with depressions. An adherence-reducing material is disposed within each depression. The adherence-reducing material reduces adherence between at least a portion of a structure and a corresponding landing pad.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Walter M. Duncan
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Publication number: 20090172485Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.Type: ApplicationFiled: March 13, 2009Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Publication number: 20090170317Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.Type: ApplicationFiled: April 9, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Kyle P. Hunt, Leila Elvira Noriega, Billy Alan Wofford, Asadd M. Hosein, Binghua Hu, Xinfen Chen