Abstract: A flow meter system includes a first ultrasonic transducer array to be flush-mounted to a pipe. The system also includes a second ultrasonic transducer array to be flush-mounted to the pipe. The system further includes a controller coupled to the first and second ultrasonic transducer arrays and configured to cause bidirectional beam steering between the first and second ultrasonic transducer arrays.

Abstract: Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region with lower doping levels toward the base contact.

Abstract: The magnitude of an output current that flows into a load is determined by placing a sense bipolar transistor and a sense resistor in series with the load, utilizing the non-linear current characteristics of the base-emitter junction of the sense bipolar transistor to compress and sense an emitter current logarithmically, and then performing an inverse log function to determine the emitter current, which is substantially identical to the output current that flows into the load.

Abstract: Relaxation oscillator circuitry is presented with low drift and native offset cancellation, including an amplifier amplifying a first current signal to provide a pulse amplifier output waveform, an integrator integrating a second current signal to provide a ramp output waveform, and a comparator comparing the integrator output waveform with a threshold set by the amplifier output waveform to generate an alternating oscillator output used to switch the polarities of the first and second current signals.

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

Abstract: One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a pulse-width modulation (PWM) signal and to control a respective at least one switch to generate an output voltage. The system also includes a feedback stage configured to generate the PWM signal based on a ramp signal and a feedback voltage that is based on the output voltage. The system further includes a ramp generator stage configured to adaptively generate the ramp signal based on the output voltage and based on the at least one activation signal.

Abstract: An optoelectronic packaged device includes stacked components within a package including a package substrate providing side and a bottom wall. The stacked components includes a comb structure on the bottom wall formed from a material having a thermal resistance > a substrate material for the bottom die providing spaced apart teeth separated by gaps. The bottom die has a top surface including electrical trace(s) and a light source die for emitting light coupled to the electrical trace and a bottom surface on the comb structure. A first cavity die is on the top surface of the bottom die or on legs of the package which extend above the bottom wall. An optics die is on the first cavity die, a second cavity die is on a sealing die which is on the optics die, and a photodetector (PD) die is optically coupled to receive light from the light source die.

Abstract: A semiconductor device comprises an array of individually controllable image pixels arranged in a plurality of reset groups. Each of the image pixels in the array of individually controllable image pixels has a one-to-one correspondence with at least one memory cell in an array of memory cells. The semiconductor device further comprises a plurality of sub-pixel sets, wherein each sub-pixel in the plurality of sub-pixel sets is a micromirror, and wherein each of the image pixels comprises a sub-pixel set.

Abstract: A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units coupled to the instruction storage memory. A first of the execution units is configured to execute instructions provided from the instruction storage memory via a first instruction path, and to execute instructions provided by a second of the execution units via a second instruction path. The second of the execution units is configured to execute instructions provided from the instruction storage memory, and to provide instructions for execution to the first of the execution units via the second instruction path. The instruction merge unit is configured to merge the instructions provided via the first and second instruction paths into a stream of instructions to be executed by the first execution unit.

Abstract: A MEMS device is formed with facing surfaces of a contoured substrate and a layer of material having complementary contours. In one fabrication approach, a first photoresist layer is formed over a substrate. Selected regions of the first photoresist layer are exposed using a patterning mask. The exposed regions of the first photoresist layer are thermally shrunk to pattern the first photoresist layer with a contour. A layer of material is formed over the contoured first photoresist layer.

Abstract: A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.

Abstract: A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison.

Abstract: A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.

Abstract: A power delivery and control device that includes a voltage input line, a voltage output line, a control logic unit coupled to the voltage input and voltage output line to control a voltage being delivered by the voltage output line based on a programmable behavior parameter, a voltage output register accessible to the control logic unit to define the programmable behavior parameter, a control register accessible to the control logic unit to activate and deactivate the voltage output line, and a control line coupled to the control logic unit to receive commands to change content of the voltage output register.

Abstract: Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power transistors used as pass elements associated with general purpose drivers. Embodiments herein prevent excessive steady-state current flow through one or more driver pass elements and/or through load elements in series with the pass element(s) via a current sensing and driver preamplifier feedback loop. A transient over-current protection circuit includes a fast transient switch and a transient over-current control circuit. The transient over-current control circuit rectifies one or more transient voltage spikes to create a momentary direct current (DC) voltage power supply (MVS) to power a fast transient driver circuit and to trip the fast transient switch. The fast transient switch discharges a transient pass element input voltage (e.g.

Abstract: An LED controller is disclosed herein. An embodiment of the controller includes a first input connectable to a power source and an output connectable to at least one light-emitting diode (LED). A power factor correction circuit is coupled between the first input and the output, wherein the power factor correction circuit operates in a first state when the power factor is corrected and wherein the power factor correction circuit operates in a second state when the power factor is not corrected. The power factor correction circuit is in the first state when no dimming of the LED is sensed, and the power factor correction circuit is in the second state when dimming of the LED is sensed.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.