Abstract: Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a first device is adapted to communicate with a second device. A clock in the first device is synchronized to a clock in the second device using beacon or/and acknowledgement frames received from the second device. A centralized guard time is calculated by the second device between two neighboring allocation intervals. The centralized guard time accounts for clock drift in the first and second devices during a nominal synchronization interval. An interval at least as long as the centralized guard time is provisioned by the second device between two neighboring allocation intervals. One or more frames are transmitted between the devices within the allocation intervals.

Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.

Abstract: Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

Abstract: Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.

Abstract: A micromachined ultrasonic transducer (MUT) circuit, which has a MUT with a MUT membrane that can vibrate back and forth to transmit an ultrasonic wave, electrically controls the movement of the MUT membrane by controllably transferring energy to the MUT membrane, thereby allowing the MUT membrane to transmit substantially any desired ultrasonic wave.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.

Abstract: A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the first die pad and terminating in a free end and a second leadframe having a second die pad and a second plurality of generally parallel leads extending outwardly relative to the second die pad and terminating in a free end. The free ends of the second plurality of leads are positioned in close nontouching adjacent relationship with the free ends of the first plurality of leads. The two leadframes may be separated from each other by a single saw cut.

Abstract: A transformer-coupled gate-drive power regulator system is provided that includes a feedback stage that generates a PWM signal having a duty-cycle that is based on a magnitude of an output voltage in an output stage. A switch driver stage configured to provide each of a first control signal and a second control signal based on the PWM signal. A switching stage comprising a first transformer input stage, a second transformer input stage, and a control switch. The first transformer input stage activates the control switch via the first control signal while the second transformer input stage is deactivated, and the second transformer input stage activates the control switch via the second control signal while the first transformer input stage is deactivated. The control switch can be configured to provide current through an output inductor in the output stage to generate the output voltage in response to being activated.

Abstract: A microelectromechanical (MEMS) device has a movable member supported above a substrate on a via support. The member and via support are fabricated integrally from first and second member forming layers. A first member forming layer forms a lower part of the member and supporting structure for the via support. First and second fill layers are deposited and patterned to form a plug that fills an inner cavity opening in the via structure. The plug is planarized to a planar part of the first member forming layer, and a second member forming layer is deposited over the first member forming layer and the planarized plug to form an upper part of the member. The via support may have a cavity filled by BARC layers.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: A lighting system includes a switch configured so that when the switch is in a first state, current from a supply flows to a light emitter, and when the switch is in a second state, current from the supply flows through the switch bypassing the light emitter. A capacitor in parallel with the light emitter provides current to the light emitter sufficient to cause the light emitter to emit light when the switch is in the second state.

Abstract: A power converter (such as a battery charger) includes a cable configured to deliver a source voltage and current to a load, where the cable is anticipated to drop some voltage as the load current increases. The power converter also includes a regulator having a feedback-adjusting transistor configured to gradually compensate for the dropped cable voltage as the load current increases. The transistor has a gate capacitance and a resistance forming an integrator configured to filter a volt-second product of an output waveshape of the converter to derive an average voltage correlated to the load current as the load current increases. The regulator is configured to increase a gate voltage of the transistor through a threshold region of the transistor and gradually turn the transistor on. The transistor is configured to apply an adjusting resistance coupled to a feedback sensing node of the regulator to increase the source voltage to compensate for the cable voltage drop and improve the load voltage regulation.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

Abstract: A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A trimmed thermal sensing system can include a temperature sensitive circuit configured to provide an output that varies as a function of temperature and in response to a trimmed bandgap reference signal. A trim network is coupled to the temperature sensitive circuit. The trim network trims the temperature sensitive circuit in an opposite direction of trimming implemented to provide the trimmed bandgap reference signal, such that temperature tolerance of the temperature sensitive circuit is reduced.