Abstract: A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

Abstract: Several circuits and methods for driver control of a switching circuit are disclosed. In an embodiment, a circuit for driver control of a switching circuit includes a driver circuit and a control circuit. The driver circuit is capable of being coupled to the switching circuit. The switching circuit includes a first switch and a second switch. The driver circuit is configured to control a conductive state of the switching circuit by facilitating an alternate state change of the first switch and the second switch. The control circuit is coupled to the driver circuit and is configured to detect a noise signal during a state change of the first switch. The control circuit is further configured to control the driver circuit to thereby slow down the state change of the first switch.

Abstract: A duty cycle correction (DCC) circuit includes a master delay line that receives an input clock and determines a period of the input clock. A calibration module is coupled to the master delay line and generates a calibration code based on a desired duty cycle and the period of the input clock. A slave delay line generates a delayed input clock based on the input clock and the calibration code. A clock generation module generates an output clock, having the desired duty cycle, in response to the input clock and the delayed input clock.

Abstract: Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency measurements utilize a reference clock. Some measurements count periods of the oscillator signal independently of the reference clock, and some measurements count periods of the reference clock independently of the oscillator signal. After one oscillator on the device has been trimmed, that trimmed oscillator may then be used to make oscillation frequency measurements for trimming another oscillator on the device.

Abstract: A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.

Abstract: Optical time domain reflectometer (OTDR) systems, methods and integrated circuits are presented for locating defects in an optical cable or other optical cable, in which a first optical signal is transmitted to the cable and reflections are sampled over a first time range at a first sample rate to identify one or more suspected defect locations, and a second optical signal is transmitted and corresponding reflections are sampled over a second smaller time range at a higher second sample rate to identify at least one defect location of the optical cable for relaxed memory requirements in the OTDR system.

Abstract: A method for in-loop filtering in a video encoder is provided that includes determining filter parameters for each filtering region of a plurality of filtering regions of a reconstructed picture, applying in-loop filtering to each filtering region according to the filter parameters determined for the filtering region, and signaling the filter parameters for each filtering region in an encoded video bit stream, wherein the filter parameters for each filtering region are signaled after encoded data of a final largest coding unit (LCU) in the filtering region, wherein the in-loop filtering is selected from a group consisting of adaptive loop filtering and sample adaptive offset filtering.

Abstract: A system for displaying a high resolution video image utilizing multiple spatial light modulators includes at least one illumination source configured to provide illumination to multiple spatial light modulators; a video data image processor coupled to receive video image data at a first visual resolution of X by Y pixels; and multiple spatial light modulators each having an image resolution lower than the first visual resolution, each configured to project an image sub-frame onto a focal plane using an image projection system; wherein the image projection system is configured to project a first sub-frame image of a first color portion while simultaneously projecting at least a second sub-frame image of a second color portion onto the focal plane, and the first and second sub-frame images are offset from one another, so that when viewed together a viewed image has at least the first visual resolution. Methods are disclosed.

Abstract: Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated therewith, wherein the cantilever vibrates when in the presence of a vibration source, and wherein the harvesting device generates a current upon vibration of the cantilever. The generated current is present at an output. A bias flip circuit is used to tune the resonant frequency of the harvesting device based on measurements of the vibration source that causes the cantilever to vibrate, wherein the bias flip circuit includes a switch that connects and disconnects an inductor to the output.

Abstract: The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment transmitters. In one embodiment, the base station transmitter is for use with a cellular communication system and includes a synchronization unit configured to provide a randomly-generated constant amplitude zero autocorrelation (random-CAZAC) sequence corresponding to a downlink synchronization signal. Additionally, the base station transmitter also includes a transmit unit configured to transmit the downlink synchronization signal using the random-CAZAC sequence. In another embodiment, the user equipment transmitter is for use with a cellular communication system and includes a reference signal unit configured to provide a random-CAZAC sequence for an uplink reference signal corresponding to a one resource block allocation of the user equipment.

Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.

Abstract: A method (and system) of determining a local binary pattern in an image includes selecting an orientation. For each pixel in the image, the method further includes determining a binary decision for each such pixel relative to one neighboring pixel of the orientation, selecting a new orientation, and repeating the determination of the binary decision for each pixel in the image relative to one neighboring pixel of the newly selected orientation.

Abstract: An amplifier (50) for voice or audio signals, and particularly for headset applications, uses a low gm amplifier (54) for initially charging an output node (OUT) at the beginning of a power-on phase. After charging the output node, a main amplifier (56) is enabled to amplify the voice or audio signal. At power-down, a sample-and-hold circuit (58) drives an output transistor to discharge an AC coupling capacitor (20). Thus, spikes at the output node are eliminated and an external filtering capacitor is not needed.

Abstract: An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.

Abstract: An inductive structure includes a power coil and a data coil. The data coil is substantially centered within the power coil. A first portion of the data coil conducts current in a first direction. A second portion of the data coil conducts current in a second direction opposite the first direction. The first portion of the data coil is connected at a node to the second portion of the data coil. The node is coupled to a ground.

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and magnitude of current at the input. A driver for the transducer includes a device having a transfer function associated with the device, the device having a device input and a device output, the device output being connectable to the input of the transducer and the device input being connectable to a power source. The device attenuates the current output at a frequency that causes a peak in the magnitude of the mechanical output of the transducer.

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Abstract: A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.