Abstract: An LLC converter having a primary side burst control circuit, and a secondary side regulator circuit. The primary side burst control circuit has an inner feedback loop circuit for adjusting the LLC operating frequency to control the power drawn by the LLC converter proportional to an optical feedback signal.

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: A device includes a charge controller to regulate a battery output voltage based on an input voltage and an input current received from a charging circuit. A loop controller monitors the input voltage and the input current to generate a feedback signal to adjust the input voltage to the charge controller.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Abstract: A method of generating an alignment matrix for a camera-radar system includes: receiving radar data originated by a radar subsystem and representative of an area of interest within a field of view for the radar subsystem; receiving image data originated by a camera subsystem and representative of the area of interest within a field of view for the camera subsystem; processing the radar data to detect features within the area of interest and to determine a reflected radar point with three dimensions relating to a camera-radar system; processing the image data to detect features within the area of interest and to determine a centroid with two dimensions relating to the camera-radar system; and computing an alignment matrix for radar and image data from the camera-radar system based on a functional relationship between the three dimensions for the reflected radar point and the two dimensions for the centroid.

Abstract: In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to the transmitter and one or more time indices of the sequence. The transmitter also include a mapping unit that transforms the sequence of reference signal bits into a complex reference signal, and a transmit unit configured to transmit the complex reference signal. In another embodiment, a receiver includes a receive unit configured to receive a complex reference signal and a reference signal decoder unit configured to detect a sequence of reference signal bits from the complex reference signal, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to a transmitter and one or more time indices of the sequence.

Abstract: In an embodiment of the invention, response validation offers increased integrated circuit security by using a unique password or re-test key for every integrated circuit manufactured. Non-invasive re-test of an IC can be performed using an encryption input.

Abstract: Systems and methods for audio power limiting based on thermal modeling are described. In some embodiments, a method includes monitoring a first temperature of a power die within an audio system; monitoring a second temperature of a digital die within the audio system; and using the first and second temperatures to limit an amplitude of an audio signal provided to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of an amplifier within the audio system to keep an operating temperature of the MOSFET under a thermal protection threshold without stopping the audio signal from being output by the audio system.

Abstract: Described examples include USB controllers and methods of interfacing a host processor with one or more USB ports with the host processor implementing an upper protocol layer and a policy engine for negotiating USB power delivery parameters, in which the USB controller includes a logic circuit implementing a lower protocol layer to provide automatic outgoing data transmission retries independent of the upper protocol layer of the host processor. The controller logic circuit further implements automatic incoming data packet validity verification and acknowledgment independent of the upper protocol layer of the host processor.

Abstract: Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.

Abstract: Methods and integrated circuits to process image data from single or multiple digital overlap (DOL) wide dynamic range (WDR) sensors, in which first received pixel data associated with a first exposure of a sensor image is stored in a DDR memory circuit, second received pixel data associated with a second exposure of the image is stored in the first buffer, third received pixel data associated with a third exposure of the image is stored in a second buffer, and fourth received pixel data associated with a fourth exposure of the image is provided to a merge circuit, and merged pixel data is stored in a dynamically partitioned line buffer for processing by an image pipeline circuit to facilitate interfacing multiple DOL WDR sensors in an interleaved fashion.

Abstract: A fault detection circuit for detecting faults in a video sequence includes a multiple input signature register (MISR) with a linear feedback shift register (LFSR) that receives pixel data for pixels in a frame region for video frames of a video sequence and receives a read signal to read the pixel data and shift the MISR; a multiple signature storage buffer (MSSB) that stores frame signatures; and a signature comparator that compares current and reference frame signatures to determine if a fault condition exists in the video sequence. The MISR holds a frame signature for the frame region of the video frame while receiving a frame end signal. The MSSB stores a current frame signature held by the MISR after receiving the frame end signal. The MSSB also stores a reference frame signature. A display processing circuit includes the fault detection circuit. An integrated circuit includes the display processing circuit.

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

Abstract: A method of Multi-Tone Mask (MTM) mode communications in a PLC network including a first router associated with a plurality of nodes. A super-frame spanning a time period is received within the subnetwork. The super-frame includes beacon frames in beacon slots within a beacon period, with each beacon frame in one of N TMs, a contention access period (CAP) including a plurality of CAP slots provided for each TM, and a poll-based contention-free period (CFP). The beacon frames provide time assignments within the super-frame including time assignments for the CAP slots and for the CFP, and TM assignments for the TMs in the CAP slots. One of nodes, another router in the subnetwork, or a router in another subnetwork transmits a broadcast frame on the PLC channel. The first router forwards the broadcast frame on the PLC channel in each of the N TMs within the time period.

Abstract: Laser speckle reduction using a passive diffuser. A diffuser for reducing laser speckle is disclosed comprising a diffuser having a colloid configured for placement in a light path of a coherent light source. The colloid exhibits Brownian motion. The diffuser can be formed of transparent plates containing the colloid. In a system for illumination, a coherent source of light outputting a light beam along a light path is provided; and a diffuser for reducing laser speckle effects is placed in the light path, the diffuser comprising a colloid disposed in a container that is transparent to the light beam output by the coherent source. A method includes illuminating a photosensitive sensor, comprising transmitting a coherent light from a light source through a diffuser comprising a colloid and directing the light from the diffuser onto the photosensitive sensor. Additional embodiments are disclosed.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A method for fabricating a micro-electro-mechanical system (MEMS) provides a semiconductor chip having a cavity with a radiation sensor MEMS. The opening of the cavity at the chip surface is covered by a plate transmissive to the radiation sensed by the MEMS. A patterned metal film is placed across the plate surface remote from the cavity.