Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.

Abstract: Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable is within an acceptable resistance range. If the load is within the acceptable resistance range, a voltage source is coupled to the load. In one embodiment one recharge interval is employed during which a capacitor is charged based, at least in part, on the voltage drop across the load and one discharge interval is employed during which a capacitor is discharged based, at least in part, on the voltage drop across the load. In a second embodiment, first and second recharge and discharge intervals are employed and prior to initiation of the recharge and discharge intervals, settling time periods are provided.

Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.

Abstract: A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.

Abstract: In one embodiment, a semiconductor structure used in manufacturing a semiconductor device includes a substrate layer. The structure also includes first and second isolation regions formed by etching an oxide layer provided on the substrate layer to define an epitaxial growth surface of the substrate layer for epitaxial growth of a substrate material on the epitaxial growth surface between the first and second isolation regions. The structure also includes an active region that includes the epitaxially-grown substrate material between the first and second isolation regions, the active region formed by epitaxially growing the substrate material on the epitaxial growth surface of the substrate layer.

Abstract: A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

Abstract: One embodiment provides a system for protecting at least one component in an integrated circuit (IC). The system includes a disconnect element that is electrically connected in series between an input terminal of the IC and the at least one component. The disconnect element is configured to have a first state to electrically connect the terminal to the at least one component and a second state corresponding to a high impedance condition that electrically isolates the terminal relative to the at least one component. A control system is configured to cause the disconnect element to transition from the first state to the second state in response to a rate of change of an input signal at the terminal exceeding a predetermined rate of change.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: A method of manufacturing an IC that comprises fabricating a semiconductor device. Fabricating the device includes depositing a photoresist layer on a substrate surface and implanting one or more dopant species through openings in the photoresist layer into the substrate, and, into the photoresist layer, thereby forming an implanted photoresist layer. Fabricating the device also includes removing the implanted photoresist layer. Removing the implanted photoresist layer includes exposing the implanted photoresist layer to a mixture that includes sulfuric acid, hydrogen peroxide and ozone. The mixture is at a temperature of at least about 130°.

Abstract: An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated during the compression.

Abstract: An integrated system comprises a light valve and an image sensor for image display and image capture. The image sensor and the light valve share a common dual-function lens by positioning the light valve and image sensor at locations offset from the optical axis of the dual-function lens.

Abstract: A screen for use in image presentations comprises an array of transmissive elongated prisms. The screen is capable of delivering incident light, having an incident angle within a specific incident angle range, to the viewing area, while preventing ambient light to be directed to the viewing area.

Abstract: Provided are a system and method for reducing failures due to hinge memory. The method, in one embodiment, includes providing a torsional element having an amount of hinge memory, wherein the hinge memory is at least partially created using an average operational temperature. The method, in this embodiment, further includes subjecting the torsional element having the hinge memory to a temperature equal to or greater than the average operational temperature while the torsional element is in a parked state for an amount of time to reduce the amount of the hinge memory.

Abstract: A spoke synchronization technique allowing for lamp-pulsing synchronizes a spoke based on sub-arrays of a spatial light modulator. The lamp pulsing occurs during the spoke synchronization; and the lamp pulse for pulsing the lamp spans substantially across the entire spoke synchronization time period.

Abstract: The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a portable computer. A portable computer (164) has an interface (172, 192, 204) that facilitates a direct connection to a portable telephone (166). The interface (172, 192, 204) electrically connects the portable telephone (166) to the portable computer (164) thus eliminating the need for a cable or tethered connection between the portable computer (164) and a portable telephone (166). In one embodiment of the invention, the portable telephone (166) is constructed to fit within a cavity (210) in the portable computer (164). When fully inserted into the computer (164), the portable telephone (166) is physically connected to the portable computer (164) by a latching mechanism and communicates with the portable computer by means of a computer/portable telephone interface (172, 192, 204 that electrically connects the portable telephone to the portable computer).

Abstract: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

Abstract: A Multi-stage noise shaping Sigma Delta Modulator (MSDM) and method of processing data using the MSDM are disclosed. The MSDM is capable of operating at high radio frequencies and is characterized by low power consumption, reduced latency and noise and occupies less area in an integrated circuit.

Abstract: A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate.

Abstract: In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the respective edges (110). In addition, seals against microcracks (150) and thermo-mechanical stress (151) are located between the vias and the active components, and sometimes also between the vias and the respective nearest edge. Workpiece (102) may be another semiconductor chip or a substrate; it has contact pads (170) matching the locations of the vias (140). The chip is vertically stacked on the workpiece so that each contact pad (170) is aligned and in electrical contact with the corresponding via (140).

Abstract: A method for providing power conservation in a processor in which, depending on the respective embodiment, a relative amount of idle time, activity time, or idle time and activity time associated with the processor are measured or detected, results of the measuring being used by the processor for controlling a clock speed. Yet other embodiments disclose, depending upon the respective embodiment, a relative amount of Input/Output (I/O), relative importance of Input/Output (I/O), and/or relative amount of time between Input/Output (I/O), associated with the processor are measured, results of the measuring being used by the processor to control power dissipation associated with the processor.