Abstract: A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).

Abstract: For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing cryptography therewith and an SoC incorporating the cryptographic accelerator or the method. In one embodiment, the cryptographic accelerator includes: (1) a key register located within the SEE and coupled to the secure memory to receive a cryptographic key therefrom and (2) data input and output registers located outside of the SEE and coupled to the key register to allow the cryptographic key to be applied to input data arriving via the data input register to yield output data via the data output register.

Abstract: The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC portion of the relaxation oscillator includes a resistance ladder and a set of momentary on pushbutton switches disposed change resistance dependent upon which key is pressed. This causes the relaxation oscillator to produce an output signal having a corresponding frequency. The counter/timer of the digital keypad processor produces a count corresponding to the oscillator frequency. The digital keypad processor latches and holds a binary number specifically identifying the depressed key. A state machine in the digital keypad processor provides transient-free, noise immune keypad decoding.

Abstract: A system for use in displaying modulated light includes a light source operable to generate a light beam. The system also includes a color wheel for receiving the light beam. The color wheel comprises a plurality of translucent segments. The plurality of translucent segments comprises a first number of blue segments, the first number of red segments, and a second number of green segments wherein the first number is greater than the second number and the second number is at least one.

Abstract: A method and system for controlling deformable micromirror devices are provided. In accordance with one embodiment of the present disclosure, a display system includes multiple deformable micromirror devices, a buffer, and a controller. Each deformable micromirror device includes a plurality of micromirrors. The buffer is communicatively coupled, at a first interface speed, to each deformable micromirror device. The buffer is operable to communicate in parallel with the deformable micromirror devices. The controller is communicatively coupled, at a second interface speed, to the buffer. The controller is operable to receive a display input and, in response, generate a plurality signals each corresponding to an optical characteristic of the display input. The controller is further operable to sequentially communicate each of the plurality of signals through the buffer to a corresponding one of the deformable micromirror devices.

Abstract: In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a switching element, the power switch being controlled by a gate signal. An inrush of the current causes an initial transient spike (ITS). A buffer having a buffer input and a buffer output is coupled to receive the gate signal and provide a buffered gate signal. The buffer output is disabled during the ITS. A sense switch (SW) is coupled to receive a portion of the current from the switching element, the SW being turned on by the buffered gate signal after the initial transient spike. A sense resistor (SR) is coupled to receive the portion of the current from the SW. An amplifier converts the portion of the current through the SR to a voltage signal for controlling the SWR.

Abstract: A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage limiter circuit. The voltage limiter generates a limited voltage. A voltage regulator is coupled to the limited voltage for generating a regulated output voltage. The voltage regulator has a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the particular computing platform (10). The manufacturer certificate may also store configuration parameters and device identification numbers. A secure run-time platform data checker (200) and a secure run-time checker (202) check the system firmware during operation of the computing platform (10) to ensure that the system firmware (30) or information in the manufacturer certificate (36) has not been altered. Application software files (32) and data files (34) are bound to the particular computing device (10) by a platform certificate (38). A key generator may be used to generate a random key and an encrypted key may be generated by encrypting the random key using a secret identification number associated with the particular computing platform (10). Only the encrypted key is stored in the platform certificate (36).

Abstract: A method and system for combining light emitted by dispersed light sources for use in a projection display or similar system. A plurality of elongated and tapered light integrators are placed side by side forming an array, each having at their small input end a light source, such as an LED. Light collimated by each light integrator is further collimated by a convex lens disposed immediately at the output end of the light integrator. From the convex lenses, the light falls upon an array integrator, preferably a fly-eye type integrator, and passes through it to a second array integrator. Light emerging from the second array integrator is then passed through one or more relay lenses and falls upon a light modulator, such as a digital mircomirror device (DMD). The modulated light beam then passes through a projection lens and onto a visual image display screen. The display screen may, for example, be the screen of a high definition television (HDTV).

Abstract: In one illustrative example, a wireless network device of a low data rate wireless personal area network (WPAN) or the like includes a controller, memory for storing one or more application programs, and a wireless transceiver coupled to the controller and operative for communications in the wireless network. The controller is adapted to receive, through the wireless transceiver, an instruction which causes the wireless device to operate as a client in performing an OAD procedure for receiving the program from another wireless device which is operated as a server in the wireless network, and to operate the wireless device as the client in performing the OAD procedure in response to such instruction.

Abstract: Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a common mode replica stage, and an amplifier is disclosed. The differential input stage exhibits an input common mode, and includes two differential inputs. A signal from the differential input stage representing the input common mode is electrically coupled to an input of the amplifier. Another input of the amplifier is electrically coupled to the common mode replica stage, and the amplifier outputs a signal indicative of the input common mode.

Abstract: One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor includes a first semiconductor fin having a first conductivity type and overlying a semiconductor body, a dielectric overlying at least part of the semiconductor fin, and a gate electrode overlying the dielectric. The memory cell also includes a diode. The diode includes an end portion of the first semiconductor fin and a second semiconductor fin that forms a junction with the end portion of the first semiconductor fin. The second semiconductor fin has a second conductivity type and includes first and second legs in different directions from the junction. Other devices and methods are also disclosed.

Abstract: An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.

Abstract: A multi-chambered system for electroplating metal layers on a semiconductor substrate. The system comprises a fluid reservoir having at least a first chamber and a second chamber. A cathode is located in the first chamber, an anode is located in the second chamber, and a shield is located between the cathode and anode. The cathode is configured to be electrically coupled to a semiconductor substrate locatable in the first chamber. The anode is configured to oppose a first major surface of the semiconductor substrate. The shield is configured to deter electrolytic fluid communication between the first and second chamber, other than though predefined openings in the shield.

Abstract: A light valve assembly comprises a holographic optical element and a light valve that comprises an array of individually addressable pixels. The light valve assemblies can be fabricated on the die level or on a wafer-level.

Abstract: An imaging system comprises a light valve having an array of light valve pixels. For processing grayscale/color images, each light valve pixel represents a discrete grayscale level. During image processing, desired grayscales can be accomplished by imaging the light valve pixels onto the target such that the perceived grayscale of each target pixel is a sum of grayscales represented by a plurality of light valve pixels.

Abstract: One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.