Abstract: A digital down converter (DDC) can be provided in a digital radio receiver front end to produce baseband I and Q signals using mixing, decimating and narrow and wide filtering dependent upon the nature of the signals. After receiving a single wide IF signal from the IF tuner, a single IF ADC converts the IF signal to digital form, and the DDC generates wide and narrow baseband I and Q signals for digital signal processing. The DDC passes wide baseband I and Q signals to a digital baseband processor, while narrow baseband I and Q signals are passed to the analog baseband processor. The system and method of the present invention permits more accurate filtering of the respective digital and analog signals, while reducing receiver complexity and cost. An analog filter in the digital radio tuner can have relaxed specifications permitted by the DDC according to the present invention.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106,and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core (105), an SRAM cell (100), and an SRAM device (400). In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core (105) that includes at least one write transistor (150). The circuitry also includes a read circuit coupled to the SRAM cell core (105) that includes at least one read transistor (185) having a gate signal in common with the gate signal of the write transistor (150). The read transistor (185) and the write transistor (150) share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor (185) differs from that of the write transistor (150).

Abstract: A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.

Abstract: A test definer, a method for automatically determining functional tests for a printed circuit board (PCB) having analog components and a test system. In one embodiment, the test definer includes: (1) a circuit builder configured to generate a representative circuit of the PCB based on schematic information thereof, (2) a circuit organizer configured to partition the representative circuit into testable sub-circuits and (3) a specification generator configured to automatically determine functionality tests for the PCB based on the sub-circuits, obtain expected values from the functionality tests and generate platform-independent specifications representing the functionality tests and the expected values.

Abstract: An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas.

Abstract: In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein the metallic layer has tapered edges with a graded transparency. The lithographic mask, along with etching processes may be used to transfer a pattern 450a into a layer of a semiconductor device.

Abstract: An apparatus is provided. The apparatus comprises a sample and hold circuit, a converter, and an adjustable current circuit. The sample and hold circuit is adapted to receive an analog input signal and to output an amplified signal. The converter is coupled to the sample and hold circuit and that converts the amplified signal to a digital signal. The controller is coupled to the converter and that receives the digital signal. The controller includes a plurality of voltage ranges, wherein each voltage range is associated with a current value, and the controller compares the digital signal to at least one of the voltage ranges to output at least one of the current values. The adjustable current circuit is coupled to the sample and hold amplifier and to the controller so that the adjustable current circuit provides a generally constant operating current that corresponds to the current value output from the controller.

Abstract: A controller and method for a switched-mode power converter adaptively provides overcurrent protection by detecting a current in the power converter exceeding a current limit during substantially a minimum on time of a power switch. A count N is computed for the number of consecutive active switching cycles that a current exceeds a current limit during substantially the minimum on time of the power switch. Conduction of the power switch is inhibited for a number of cycles that is a function of the count N, which is an increasing function of N. The function of the count N is preferably the function 2N?1. The count N is reset to zero if the current in the power converter does not exceed the current limit substantially during the minimum on time of the power switch. The controller can be easily implemented with a digital integrated circuit for a wide range of applications.

Abstract: A system and method for generating a message integrity code, MIC, for a MAC protocol data unit in a wireless local area network, WLAN, operating according to the IEEE 802.11 standard. A MAC service data unit, MSDU, sequence control sequence number, SN, input to the MIC algorithm is suppressed, e.g. set to all zeros, when calculating the MIC. Only the fragment number, FN, portion of the sequence control is included in calculation of the MIC. The MIC may therefore be calculated before an actual SN has been determined. All MPDUs include sequential packet numbers, PNs. A station receiving MPDUs checks the PNs of MPDUs having the same SN, and rejects messages which do not have a proper sequential set of PNs.

Abstract: A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit includes a first current source circuit for supplying a first current through a reference resistor. A second current source circuit supplies a second current through the first variable resistor. In operational amplifier has a first input coupled to a first conductor connecting the first current source to the reference resistor, a second input coupled to a second conductor connecting the current source to the first variable resistor, and an output applying the first resistance control signal to a control terminal of the first variable resistor, to force the resistance of the first variable resistor to be equal to a resistance of the reference resistor. The resistance of a second variable resistor of an attenuator is controlled in response to the resistance control signal.

Abstract: The first stage of a plurality of stages in a pipelined analog to digital converter couples its input analog signal to both a first and second sample and hold (S/H). The first S/H output is coupled to the input of a multiplying digital to analog converter (MDAC) of the first stage, and the second S/H output is coupled to a flash ADC of the first stage. The delay of the second S/H is longer than the delay of the first S/H, and the clock edge of the second S/H is delayed an adjustable amount with respect to the clock edge of the first S/H, so as to minimize the difference in held voltages at the outputs of the two S/Hs in the presence of an input signal having high slew rate. The residue voltage of the first stage is amplified in the MDAC by 2^(n?2) where n is the number of bits in the stage.

Abstract: A receiver for a wireless local area network, WLAN, having a low power listening mode of operation. The receiver includes two separate paths in the analog front end, AFE. One path includes a low resolution and low power analog to digital converter, ADC. The other path includes a high resolution and high power ADC. In listen mode, only the low resolution ADC is powered and provides inputs to a packet detector for identifying a barker code. When the correct barker code is received, the high resolution ADC is enabled and coupled to a receiver for receiving a payload in the data packet.

Abstract: A disk drive controller including a differential voice coil motor control function is disclosed. The differential voice coil motor control function includes an on-chip compensation network for the inner control loop, including a resistor formed of one or more MOS transistors connected in series. The gate of the MOS transistors in the compensation network is driven with a bias voltage based on a tuning current, where the tuning current is derived so that it varies with process and temperature variations of the integrated circuit, for example with variations in an on-chip capacitor. The on-chip compensation network can be tuned with sufficient precision to properly compensate the inner control loop to provide the desired frequency response in driving the voice coil motor in the disk drive.

Abstract: System and method for creating single stud bumps having an increased stand-off height. A preferred embodiment includes a method of using a capillary for creating stud bumps in a flip chip assembly, the capillary includes a hole section adapted to pass a wire, a chamfer section providing a transition from the hole section to a stud bump section, and a sidewall within the stud bump section, the sidewall having a sidewall height, wherein the side wall height is equal to, or greater than, the a diameter of the stud bump section.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

Abstract: A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element.

Abstract: Contention communications often requires a station to wait an inordinate amount of time before the station is able to transmit its data successfully. In many applications, an extended delay is not acceptable. Contention-free communications in a contention period allows a hybrid coordinator (HC) to schedule contention-free access to a communications medium so that extended delays may be eliminated, and to coordinate contention access to the medium so that better throughput and delay performance is achieved. A method for creating contention-free communications within a contention communications period is presented, along with adaptive algorithms for contention access during the same contention period.