Abstract: This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

Abstract: A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency (RF) amplifier configured to produce an RF signal or an RF receiver configured to receive an RF signal is formed on the top surface of the substrate. A through-substrate via is coupled to an output of the RF amplifier. A metalized antenna formed on the bottom surface of the substrate is coupled to the through-substrate via. The metalized antenna is configured to launch an electromagnet wave representative of the RF signal into a dielectric waveguide (DWG) when the DWG is coupled to the bottom side of the substrate.

Abstract: A video encoder includes a buffer, a DMA engine, a motion estimator and a motion compensator. The buffer includes four pages where macroblocks are stored. The motion estimator generates a motion vector for a given macroblock. The motion compensator applies the motion vectors generated by the motion estimator to a previously encoded frame. Each of the four pages is concurrently accessed by one of the motion estimator, the motion compensator, and a channel of the DMA engine. Simultaneously the motion compensator accesses one page of the buffer containing a first set of macroblocks, the motion estimator accesses a second page of the buffer containing a second set of macroblocks, a first DMA engine channel writes a different set of macroblocks to a third page of the buffer and a second DMA engine channel writes another set of macroblocks to a fourth page of the buffer.

Abstract: A power converter sub-assembly/module includes a power switching assemblage defining a cavity within which can be mounted a driver IC. The power switching assemblage includes a load inductor component stack attached to a power transistor block and an interconnect spacer block, defining a cavity between the two blocks. The power transistor block includes a high and low side FETs attached side-by-side to a switch-node metal carrier that includes an attach-surface opposite the FETs. The power switching assemblage is mountable to an interconnect surface that includes connection pads VIN, VOUT, GND, HG (high-side gate) and LG low-side gate). For a module configuration, the power switching assemblage is combined with a driver IC that provides high (HG) and low (LG) gate drive—the power switching assemblage and the driver IC are mounted to a module interconnect substrate, with the driver IC mounted within the cavity of the power switching assemblage.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: Systems and methods for compensating angular misalignment in Optical Image Stabilization (OIS) systems are described. In some embodiments, a method may include measuring an angle representing a misalignment between an actuator and an electronic component within a camera; and compensating for the misalignment using a rotation matrix, wherein the rotation matrix is calculated based upon the angle. In other embodiments, a camera may include an image sensor coupled to a Printed Circuit Board (PCB); an OIS actuator coupled to the PCB and optically coupled to the image sensor, where the OIS actuator is physically misaligned with respect to the image sensor; and a controller coupled to the PCB, the controller configured to: measure an angle representing the misalignment; and compensate for the misalignment using a rotation matrix at the time of an image capture, where the rotation matrix is calculated based upon the angle.

Abstract: Several circuits and methods for driver control of a switching circuit are disclosed. In an embodiment, a circuit for driver control of a switching circuit includes a driver circuit and a control circuit. The driver circuit is capable of being coupled to the switching circuit. The switching circuit includes a first switch and a second switch. The driver circuit is configured to control a conductive state of the switching circuit by facilitating an alternate state change of the first switch and the second switch. The control circuit is coupled to the driver circuit and is configured to detect a noise signal during a state change of the first switch. The control circuit is further configured to control the driver circuit to thereby slow down the state change of the first switch.

Abstract: In one form of invention a process of operating a host computer coupled to a communications network including: determining whether a diversity flag is set, when a communications connection is requested; sending a request from the host computer to a proxy identification list server in a communications network for proxy pair identification information, when the diversity flag is set; receiving in the host computer the proxy pair identification information from the proxy identification list server in response to the host request; and wherein the sending includes communicating from the host computer to a destination computer though a first communication path that includes a first proxy device and though a second communication path, separate from the first communication path, that includes the second proxy device.

Abstract: A circuit and method for providing a fully integrated differential boost converter and amplifier. A first half bridge circuit has a first output node and a first switching node. A second half bridge circuit has a second output node and a second switching node. A capacitive load is coupled between the first output node and the second output node. An inductor is coupled between the first switching node and the second switching node. Control modes are provided to couple the first output node to a supply voltage and the first switching node to ground; to couple the first output node to the supply voltage and the second switching node to ground; to couple the second output node to the supply voltage and the first switching node to ground; and to couple the second output node to the supply voltage and the second switching node to ground.

Abstract: Systems and methods of wireless power transfer system with interference detection disclosed herein detects possible excessive energy transfer associated with parasitic metal objects placed in close proximity with system coils by comparing power received on the receiving side of the system with the power consumed on the primary side considering known losses in the system. If the result of such comparison shows that power consumed on the primary side substantially exceeds power received on the secondary side, the system may terminate operation.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: The present disclosure provides a receiver, a transmitter and methods of operating a receiver or a transmitter. In one embodiment, the receiver includes a receive unit configured to receive transmissions from multiple antennas. The receiver also includes a rank feedback unit configured to feed back a transmission rank selection, wherein the transmission rank selection corresponds to a transmission rank feedback reduction scheme. The receiver further includes a precoding feedback unit configured to feed back a preceding matrix selection, wherein the preceding matrix selection corresponds to a preceding matrix feedback reduction schemes.

Abstract: Hybrid magnetic current sensors and sensing apparatus are presented with closed-loop and open-loop circuitry employs first and second integrated magnetic sensors to sense a magnetic field in a magnetic core structure gap to provide high accuracy current measurement via a closed-loop magnetic circuit with the first sensor in a nominal current range as well as open-loop current measurement using the second sensor in an extended second range to accommodate over-current conditions in a host system as well as to provide redundant current sensing functionality.

Abstract: A synchronization circuit receives an external clock input. The circuit includes an internal oscillator; a clock detection circuit, coupled to the external clock input, for determining whether a clock signal at the external clock input is valid; circuitry for keeping the frequency of the internal oscillator constant until the clock detection circuit determines that an external clock signal is valid; and circuitry for switching the output of the synchronization circuit from the internal oscillator to the external clock input when the clock detection circuit determines than an external clock signal is valid.

Abstract: An integrated circuit includes logic configured to generate scrambling sequences, each based on a different scrambling seed, for a smart-utility-network data packet communication. A Hamming distance between any two scrambling sequences is half the length of a PSDU of the data packet or greater.

Abstract: A circuit includes an amplifier circuit that receives a residue voltage from an output capacitor connected to an output of a digital to analog converter (DAC). The DAC is employed in a pipeline stage of an analog to digital converter (ADC). The amplifier circuit provides a scaled output voltage based on the residue voltage. A sample circuit samples the scaled output voltage during a first portion of a hold phase of the DAC. A discharge circuit supplies the sampled scaled output voltage to the output of the DAC during a second portion of the hold phase of the DAC to mitigate settling time of the DAC.