Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A novel apparatus and method of reduced power consumption for battery backup operation of a communication device such as a cable modem. When the cable modem senses a failure of the external power source it requests from the cable head-end to switch from multi-channel DOCSIS 3.0 operation to single-channel DOCSIS 2.0 operation. In response to approval by the cable head-end, the cable modem shuts down multi-channel circuits in the PHY such as the wideband analog to digital converter (ADC) which is normally used during multi-channel operation. In its place, it activates narrowband circuitry such as a narrowband ADC which consumes far less power. Tuner filter circuits are also swapped to match the reduced bandwidth requirements of battery backup operation. To further reduce power, the narrower bandwidth requirements during battery backup operation permit the linearity of a programmable gain amplifier (PGA) in the upstream path to be reduced.

Abstract: Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such that prevailing force of gravity may be used to assist in the removal of contaminants from the wafer.

Abstract: A device and a method of characterizing a communications channel. The method includes transmitting a first part of a packet preamble using two or more antennas and transmitting a second part of the packet preamble using the two or more antennas. Each antenna transmits an orthogonal encoding of the second part of the packet preamble. The method also includes transmitting a packet header using the two or more antennas and transmitting a packet payload using the two or more antennas. Each antenna transmits an orthogonal encoding of the packet header. The packet payload may be encoded across the transmissions of the two or more antennas.

Abstract: Various embodiments of a rear-projection screen, a method of rear-projection collimation and a projection video display (PVD) system. In one embodiment, a rear-projection screen includes: (1) a total-internal-reflection (TIR) fresnel lens configured to aim light received at an incidence angle toward a central axis of the TIR fresnel lens at a convergence angle and (2) a refractive fresnel lens configured to refract the light received from the TIR fresnel lens and at least to reduce the convergence angle.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.

Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.

Abstract: A method of tilting a micromirror includes providing a substrate, a sloped electrode outwardly from the substrate, and a sloped electrode positioning system outwardly from the substrate. The method also includes applying, by the sloped electrode positioning system, forces sufficient to position the sloped electrode in an orientation that slopes away from the substrate.

Abstract: Methods and apparatus to detect an over-current in switching circuits are described. An example method to detect an over-current in a switching circuit includes randomly selecting a sensor from a plurality of sensors operatively coupled to an output stage of the switching circuit; detecting a first voltage via the randomly selected sensor; and comparing the first voltage to a reference voltage to generate a signal, wherein the signal indicates a status of the output stage of the switching circuit.

Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.

Abstract: An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.

Abstract: Methods to implement power control in a digital power amplifier are described.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

Abstract: A trace test and debug system for a target processor generates a program counter trace stream, a timing trace stream and a data trace stream. The target processor has three states, a program code execution state, an interrupt service routine code execution state, and a state where code execution is halted. The trace streams can be controlled so that the timing trace stream can be generated or excluded during the code execution halts. Similarly, when the timing trace stream is enabled for the interrupt service routine(s), the program counter and data trace streams can be selectively generated or excluded. The contents of the pipeline flattener can be held or flushed code execution halt depending on whether the pipeline is unprotected or protected. When the contents of the pipeline flattener are held during a code halt, the program counter trace stream and data trace stream is halted even if the timing trace stream remains active.

Abstract: A radio such as a frequency division duplex (FDD) radio (100) has a first local oscillator (LO1I and LO1Q) that is set to coincide with the transmitter section's (126) center frequency or a sub-harmonic thereof. In this way, after the first down-conversion, the transmit interferer is converted to DC, where it can be effectively removed using a simple high-pass filter (110, 112) such as a DC blocking capacitor. Image rejection is achieved by the use of a two-step down-conversion approach that uses quadrature local oscillators to implement a single-sideband down-converter.

Abstract: In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single terminal, whereby providing a terminal for the exchange of other signals with the integrated circuit. Using the same signals for test and system clocks allows selected components to be eliminated.