Abstract: A reflective and deformable micromirror device comprises a reflective micromirror plate attached to a deformable hinge that is formed on and held by a hinge post on a substrate. The substrate has an addressing electrode formed thereon. A selected dielectric material is disposed between the deformable hinge and the addressing electrode.

Abstract: Disclosed is an optical component, which comprises a prism element adjacent to a lens element, where the two elements are separated by a small air gap. In disclosed embodiments, the elements have adjacent and parallel surfaces which are substantially planar and which, with the small air gap, operate through Total Internal Reflection (“TIR”) to direct light beams that strike the planar surfaces. Light beams that strike at less than the critical angle are internally reflected, while light beams which strike at greater than the critical angle pass through. The TIR surfaces thereby separate the desired optical signals from the spurious ones. The combined TIR prism lens operates as a single and integrated component which directs desired light beams to a reflective optical processing element such as a Spatial Light Modulator and which focuses the processed light beams as they leave the combined TIR prism lens.

Abstract: An integrated system comprising both imaging and computing capabilities comprises a light valve and a CPU, as well as other functional members for performing computing and imaging.

Abstract: Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A power controller and physical link controller for the port share a high speed communication link to transfer information and control instructions from one to the other. The physical link controller provides digital functionality and processing capabilities that can generate power control instructions sent to the power controller over the high speed link. The power controller provides analog functionality for controlling the power supplied to the network connection and transfers power related information to the physical link controller over the high speed communication link and receives control instructions through a digital interface. The separation of digital of analog functionality simplifies the power control circuitry, removes redundancy, and frees valuable circuit board space for other desired functionality.

Abstract: The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.

Abstract: A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through the first and second reference circuit blocks respectively, an amplifier having non-inverting and inverting inputs responsive to the voltages developed by the first and second reference circuit blocks respectively and having an output connected to control the currents provided by the first and second current sources, and an output stage having a reference output controlled by the output of the amplifier. The reference circuit further comprises start-up circuitry, including a latch having an output indicating its state and being responsive to a signal indicative of the output from the reference output to latch from a first state into a second state when that signal passes a first threshold, and a switch that is responsive to the output of the latch to supply a control signal.

Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Abstract: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate.

Abstract: An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.

Abstract: An apparatus for selectively coupling a system with a first power supply or a second power supply includes: (a) a first switch for effecting a first coupling of the system with the first power supply; (b) a second switch for effecting a second coupling of the system with the second power supply; (c) a first switch control unit coupled for controlling the first switch; (d) a second switch control unit coupled for controlling the second switch; (e) a connection director unit coupled with the first and second switch control units for providing control signals to effect the first and second coupling; at least one of the first and second coupling being effected as an initial coupling establishing a generally time-dependent increasing current between the system and one power supply and a continuing coupling establishing a substantially constant operating current between the system and the one power supply.

Abstract: In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle pattern (602) that is configured by arranging the dies in an array having m rows and n columns, where the m rows start in a row adjacent to the orientation marker (606), and m and n are integers. The reticle pattern (602) is transferred to the full wafer (600) to sequentially form a portion of the dies. The transferring includes placing an inkless marker (620) in the form of one or more non-circuit dies between the n columns of adjacent reticle patterns. The reticle pattern (602) is repeatedly transferred to form a remaining portion of the dies to complete the full wafer (600). A wafer map for the full wafer (600) is stored, with the wafer map including a non-circuit bin containing data describing the inkless marker (620).

Abstract: A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Abstract: An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including information-indicating signal values; includes: (a) an input locus for receiving the received signal; (b) an output locus for presenting the output signal; (c) a first signal-handling circuit coupled with the input locus and with the output locus and setting the second reference level at the output locus; and (d) a second signal-handling circuit coupled with the input locus and with the first signal-handling circuit; the first signal-handling circuit and the second signal-handling circuit cooperating to convey the information-indicating signal values from the input locus to the output locus.

Abstract: A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference voltage and a drain coupled to the inductor, and a second transistor having a source coupled to an output conductor to produce an output voltage and a drain coupled to the inductor. A feedback signal representative of a value of the output voltage is generated, and a switch control signal is produced in response to the input voltage and a second reference voltage. The second transistor is turned off in response to the switch control signal each time the inductor current has decayed to zero to prevent reverse current flow through the inductor. A regulating signal indicates whether or not the feedback voltage exceeds the second reference voltage, to regulate the output voltage in a pulse-frequency modulation mode.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: Audio cross-talk cancellation by inverse HRTF matrix only for low frequencies; high frequencies rely upon the natural barrier of a listener's head. The low frequency cutoff is determined by a peak in the inverse matrix of the head-related transfer functions.

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

Abstract: A non-specular reflective optical element comprises a reflective surface. A beam of incident light can be reflected such that the reflective angle may or may not be the same as the incident angle. In an exemplary application of a rear projection system, the non-specular folding mirror is used to project the modulated light from a light valve onto a translucent screen.

Abstract: According to an aspect of the present invention two streams data encoding corresponding information contained in a multimedia signal are generated with one bitstream (“first stream”) providing for reproduction of the information with a base quality (e.g., according to a corresponding standard), and the second bitstream (“second stream”) containing information which can be used to further enhance the quality of reproduction.

Abstract: The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially (SPER) (110). The non-amorphizing tail implant is generally annealed (106) before a doped amorphous layer for SPE is formed (107). SPE provides a high active dopant concentration in a shallow layer. The non-amorphizing tail implant (105) expands the source/drain extension region beyond the range dictated by the SPE-formed layer and keeps the depletion region of the P-N junction away from where end-of-range defects form during the SPE process. Thus, the SPE-formed layer primarily determines the conductivity of the junction while the tail implant determines the location of the depletion region. End-of-range defects form, but are not in a position to cause significant reverse bias leakage.