Abstract: A polishing pad for polishing a semiconductor wafer or other materials, having grooves in the polishing pad to enhance the usable lifetime of the polishing pad.

Abstract: A method and apparatus are provided. The VBUS conductor is checked to determine whether the voltage on the VBUS conductor is greater than a vSafe0V voltage within a dead battery detect time interval, and the device policy manager is instructed to apply a vSafeDB voltage to the VBUS conductor if the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a bit stream detect timer interval. If the bit stream is not detected within the bit stream detect timer interval, then the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager is instructed to apply a vSafe5V voltage to the VBUS conductor if the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. If the bit stream has stopped within the device ready timer interval, then the policy engine sends capabilities as a source port.

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract: Systems, apparatus and methods are presented for sensing or estimating a tilt angle, in which a current flowing in an eccentric mass motor is sensed, and a detector circuit assesses the amplitude of a synchronous component of the motor current and provides an output signal or value indicating a tilt angle relative to a gravitational axis at least partially according to the amplitude of the synchronous component of the motor current.

Abstract: A power supply circuit, suitable for use in an integrated circuit, the circuit configured to detect whether an output voltage has been specified using an external resistance network. The power supply circuit is configured to determine the appropriate output voltage to be generated based on a voltage measured at a single input pin of the power supply circuit, where the single input pin provides a feedback voltage used in the control loop of the power supply circuit. Based on the feedback voltage at the input pin, the power supply circuit is configured to detect the presence of a resistance network external to the single input pin. If an external resistance network is detected, the power supply is configured to generate the output voltage specified at the input pin. If no external resistance network is detected, the power supply is configured to generate a default output voltage.

Abstract: Embodiments of the invention provide methods for key fob to control unit verification, retention, and revocation. After an initial pairing between a key fob and a control unit, the devices share a secret operation key (OpKey). For verification, the key fob sends the 8 lowest-order bits of a 128-bit counter and some bits of an AES-128, OpKey encrypted value of the counter to the control unit. For key revocation and retention, the control unit is prompted to enter an OpKey retention and revocation mode. Subsequently, each of the remaining or new key fobs is prompted by the user to send a verification message to the control unit. When the control unit is prompted to exit the OpKey retention and revocation mode, it retains the OpKeys of only the key fobs that sent a valid verification message immediately before entering and exiting the OpKey retention and revocation mode.

Abstract: Visual codes are scanned to assist navigation. The visual code may be a Quick Response (QR) code that contains information useful to calibrating a variety of navigation-based sensors such as gyroscopes, e-compasses, and barometric pressure sensors.

Abstract: A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and throttling the trace data stream to ensure that the bandwidth available for the trace data stream is not exceeded. A trace data gap is inserted into the data stream to indicate the amount and type of data discarded during the throttling process.

Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: A plastic package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package; each pin has a long axis, the long axes of the pair forming a non-orthogonal angle. Package further includes a chip assembly pad, acting as a thermal spreader and semiconductor chip.

Abstract: Several methods and systems for facilitating multimedia data encoding are disclosed. In an embodiment, a plurality of picture buffers associated with multimedia data are received in an order of capture associated with the plurality of picture buffers. Buffer information is configured for each picture buffer from among the plurality of picture buffers comprising at least one of a metadata associated with the corresponding picture buffer and one or more encoding parameters for the corresponding picture buffer. A provision of picture buffers in an order of encoding is facilitated based on the configured buffer information.

Abstract: An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a protective layer over the first and second electrodes. The protective layer has a first opening that exposes a portion of the first electrode and a second opening that exposes a portion of the second electrode. The apparatus further includes a first electrical contact at least partially within the first opening and electrically coupled to the first electrode. In addition, the apparatus includes a second electrical contact at least partially within the second opening and electrically coupled to the second electrode. Each of the first and second electrical contacts includes a stack of metal layers. The stack of metal layers includes a titanium nitride layer, a titanium layer over the titanium nitride layer, and an aluminum copper layer over the titanium nitride layer and the titanium layer.

Abstract: A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract: A packaged semiconductor device (100) comprising a leadframe having a pad (101) with an assembled semiconductor chip (110), a plurality of straps (102) connecting the pad to side edges of the device package, leads (103), and a package (150) of plastic compound adhering to the leadframe; at least one surface (102a) of the straps covered with a layer (120) of a compound both non-adhesive to polymeric compounds and hydrophobic; the compound (220) selected from a group including fluorinated thiol compounds, fluorinated amine compounds, fluorinated aminesilanes, organosilanes, and their derivatives; or the compound (330) selected from a group including open-pore microcellular metal foams and polymer foams. Further, the package may include an array of holes through the plastic compound, extending from the package surface to the strap surface.

Abstract: A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low side power switch (LSA) and a second half-bridge. A transfer capacitor (Ct) is connected in series with HSA and LSA, and between the first and second half-bridges. An adaptive HS driver circuit has an output coupled to a gate of HSA and includes a power supply circuit including a summing circuitry that dynamically outputs a variable power supply level (VGX) based on a fixed voltage and a voltage across Ct, a buffer driver, and a boost capacitor (CA) across the buffer driver. VGX is coupled to a positive terminal of CA. The power supply circuit is configured so that as a voltage across Ct varies, VGX adjusts so that a voltage across CA is changed less than a change in voltage across Ct.

Abstract: A system for detecting tamper events in a digital circuit by having a Critical Path Replica (CPR) circuit operable in parallel with the circuit being monitored, and adjusted to generate a timing violation if the operating parameters of the circuit change to be outside the normal operating parameters. The critical path replica circuit is adjusted to generate a timing violation before the actual circuit being monitored fails due to the changed operating parameters.

Abstract: An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface.