Abstract: An electronic system comprises a first chip (101) of single-crystalline semiconductor including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab 130 bordered by retaining walls 131 and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Abstract: A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna.

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract: A pulse generator generates a square-wave pulsed signal that has a variable pulse width. The pulse width, which is defined by the delay through a delay line, varies in response to variations in an input voltage, as well as in response to phase differences between a reference clock signal and a trigger signal.

Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the endian view used by each individual processor within the attached subsystem, and can perform the appropriate endian conversion on each processor's transactions to adapt the transaction to/from the endian view used by the interconnect.

Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.

Abstract: A semiconductor device comprises a semiconductor wafer; a piezoelectric resonator formed on the wafer, and an active circuit also formed on the wafer. The active circuit (e.g., a frequency divider) is electrically connected to the piezoelectric resonator.

Abstract: Disclosed herein is a die eject assembly for a die bonder that may include a poker pin having an elongate shaft portion with a first end and a second end. The poker pin further includes a base portion having a first end and a second end. The base portion has a maximum diameter that is larger than the maximum diameter of the elongate shaft portion. The elongate shaft portion first end is fixedly attached to the base portion second end.

Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

Abstract: The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output.

Abstract: A duty cycle correction (DCC) circuit includes a master delay line that receives an input clock and determines a period of the input clock. A calibration module is coupled to the master delay line and generates a calibration code based on a desired duty cycle and the period of the input clock. A slave delay line generates a delayed input clock based on the input clock and the calibration code. A clock generation module generates an output clock, having the desired duty cycle, in response to the input clock and the delayed input clock.

Abstract: A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes.

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A rotational resolver system and method includes a rotational shaft to which at least one eccentric conductive coarse resolution disc is fixed and to which at least one conductive fine resolution disc is also fixed. The fine resolution disc defines a plurality of generally semicircular protruding edge segments. At least one conductive coarse-disc sensing coil is disposed adjacent an edge of the coarse resolution disc, and at least one conductive fine-disc sensing coil is disposed adjacent the edge of the fine resolution disc.

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an interface surface configured for interfacing to the mating end of the DWG. A conductive layer is etched to form a dipole antenna disposed adjacent the interface surface. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. A set of director elements is embedded in the mating end of the DWG. Specific spacing is maintained between the dipole antenna and the set of director elements.

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract: In an electronic device, an RC oscillator generally includes a resistor, a capacitor and at least one inverter. The resistor and capacitor generate a time-varying voltage. The time-varying voltage is provided to the at least one inverter to cause a clock signal to propagate therethrough. The clock signal propagates with a time delay that is at least partially dependent on a supply voltage. The supply voltage is adjusted to maintain the time delay at almost a constant value.

Abstract: This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

Abstract: Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC device, such as a PLC gateway, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, terminating transmissions to the PLC network for a network-specific co-existence Extended Interframe Space (cEIFS) time period in response to the foreign preamble, and resuming transmissions to the PLC network after expiration of the network-specific time period.