Abstract: In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A transformer includes first and second coils. A first terminal of the first coil is coupled through a first resistor to the first line. A second terminal of the first coil is coupled through a second resistor to the second line. A first terminal of the second coil is coupled through a third resistor to the third line. A second terminal of the second coil is coupled through a fourth resistor to the fourth line.

Abstract: Channel state information (CSI) feedback in a wireless communication system is disclosed. User equipment transmits a CSI feedback signal via a Physical Uplink Control CHannel (PUCCH). If the UE is configured in a first feedback mode, the CSI comprises a first report jointly coding a Rank Indicator (RI) and a first precoding matrix indicator (PMI1), and a second report coding Channel Quality Indicator (CQI) and a second precoding matrix indicator (PMI2). If the UE is configured in a second feedback mode, the CSI comprises a first report coding RI, and a second report coding CQI, PMI1 and PMI2. The jointly coded RI and PMI1 employs codebook sub-sampling, and the jointly coding PMI1, PMI2 and CQI employs codebook sub-sampling.

Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.

Abstract: Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates frames to be transmitted to a destination node in the PLC network. A processor in the node is configured to generate a data payload comprising data to be sent to the destination node. The processor divides the data payload into two or more payload segments and encrypts the payload segments. The processor creates a frame for each of the encrypted payload segments, wherein each frame comprises a message integrity code. The processor creates a segment identifier for each frame using the message integrity code and an authentication key that is shared with the destination PLC node. The segment identifier is added to each frame.

Abstract: Methods for improved parallel motion estimation are provided that decouple the merging candidate list derivation and motion estimation for merge mode and skip mode and the advanced motion vector predictor (AMVP) candidate list construction from regular motion estimation to increase the coding quality in parallel motion estimation while meeting throughput requirements. This decoupling may be accomplished by modifying the availability rules for spatial motion data (SMD) positions for construction of the candidate lists. As part of the decoupling, largest coding units (LCUs) of a picture may be divided into non-overlapping parallel motion estimation regions (PMER) of equal size. Within a PMER, motion estimation for merge mode, skip mode, and normal inter-prediction mode may be performed in parallel for all the prediction units (PUs) in the PMER.

Abstract: A molded system (100) has a plurality of components (110, 120, 130) attached to a carrier (101), one of the components being an object (110) of irregular thermal capacitance. For example, carrier (101) may be a QFN/SON-type leadframe and object (110) an inductor of high thermal capacitance. The surface of the object is sealed with a hardened polymeric layer (220) of high thermal resistance, whereby the layer (220) thermally insulates the object (110) and inhibits the transport of thermal energy between the object and the system. System (100) has molding compound (140) encapsulating the carrier and the attached components including the object (110) and the polymeric layer sealing the object's surface.

Abstract: An apparatus for detecting misplaced units in a moving carrier tape having a plurality of pockets with units positioned therein. The apparatus includes a displaceable assembly having a head portion positioned above the carrier tape that is adapted to deflect in response to engagement with a misplaced unit in one of the plurality of pockets.

Abstract: An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces.

Abstract: A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and magnitude of current at the input. A driver for the transducer includes a device having a transfer function associated with the device, the device having a device input and a device output, the device output being connectable to the input of the transducer and the device input being connectable to a power source. The device attenuates the current output at a frequency that causes a peak in the magnitude of the mechanical output of the transducer.

Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Abstract: A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU.

Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A time-of-flight sensor device generates and analyzes a high-resolution depth map frame from a high-resolution image to determine a mode of operation for the time-of-flight sensor and an illuminator and to control the time-of-flight sensor and illuminator according to the mode of operation. A binned depth map frame can be created from a binned image from the time-of-flight sensor and combined with the high-resolution depth map frame to create a compensated depth map frame.

Abstract: In response to a signal failing to exceed an estimated level of noise by more than a predetermined amount for more than a predetermined continuous duration, the estimated level of noise is adjusted according to a first time constant in response to the signal rising and a second time constant in response to the signal falling, so that the estimated level of noise falls more quickly than it rises. In response to the signal exceeding the estimated level of noise by more than the predetermined amount for more than the predetermined continuous duration, a speed of adjusting the estimated level of noise is accelerated.

Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.

Abstract: Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer (120), and a second chip (130) with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad (107) has a portion (107a) recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.

Abstract: Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1).

Abstract: A power supply system includes a rechargeable battery to deliver a supply current to a load and a circuit to limit a discharge current when the rechargeable battery is supplying power to the load. The power supply system may further include an integrator for integrating a discharge voltage representing the discharge current that exceeds a predetermined limit, a pulse-width-modulation (PWM) circuit for producing a control signal having a PWM duty cycle representing the discharge voltage, and a driver circuit for delivering the supply current to said load according to said control signal. In one embodiment, a digital register is used to set the battery discharging current limit, in another embodiment an analog circuit is used to set the battery discharging current limit, and in yet another embodiment or a combination of the digital register and analog circuit is used to set the battery discharging current limit.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.