Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.

Abstract: A segmented bipolar transistor includes a p-base in a semiconductor surface including at least one p-base finger having a base metal/silicide stack including a base metal line that contacts a silicide layer on the semiconductor surface of the p-base finger. An n+ buried layer is under the p-base. A collector includes an n+ sinker extending from the semiconductor surface to the n+ buried layer including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap which cuts a metal line and/or the silicide layer of the stack.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

Abstract: A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined bit pattern is matched and a fixed step size for the final read meets the PMR.

Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.

Abstract: A system includes a permanent magnet motor having a rotor and a stator. The rotor and the stator have a configuration that causes the motor to generate a back-electromagnetic force (EMF) waveform that is substantially sinusoidal. The system also includes a motor controller having a sliding-mode observer configured to identify the back-EMF waveform and a position observer configured to estimate at least one characteristic of the motor using the identified back-EMF waveform. The stator may include multiple teeth projecting towards the rotor and multiple conductive windings, where each conductive winding is wound around a single tooth. The rotor may include multiple magnetic poles, where each magnetic pole has a span of about 60° or less. The sliding-mode observer may be configured to receive current measurements associated with three-phase signals and voltage commands generated by the motor controller. The position observer may include a proportional-integral (PI) regulator.

Abstract: A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect.

Abstract: At least some of the embodiments are methods including detecting low user dynamics by a first MEMS sensor, determining a first sensor sampling rate value corresponding to the low user dynamics wherein the first sensor sampling rate value is less than a second sensor sampling rate value corresponding to high user dynamics, and adjusting a sampling rate of a second MEMS sensor to the first sensor sampling rate value.

Abstract: A wireless combination (combo) device is coupled to an antenna for communicating via a first wireless network over a first band. A packet aggregator is coupled to the first wireless transceiver configures a frame aggregated packet for at least a portion of activities on the first wireless network. The frame aggregated packet includes a plurality of data packets and a dummy packet or spoofing so that said frame aggregated packet is extended in time or indicates an extension sufficient to overlap a Tx time interval or Rx time interval for communications occurring over a second wireless network. The first wireless network and said second wireless network are overlapping networks.

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract: A hermetic package comprising a substrate (110) having a surface with a MEMS structure (101) of a first height (102), the substrate hermetically sealed to a cap (120) forming a cavity over the MEMS structure; the cap attached to the substrate surface by a vertical stack (130) of metal layers adhering to the substrate surface and to the cap, the stack having a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance (140); the stack having a bottom metal seed film (131) adhering to the substrate with a first width (131a), and further a top metal seed film (132) adhering to the cap with a second width (132a) smaller than the first width, the top metal seed film tied to a layer (135) including gold-indium intermetallic compounds, layer (135) having a height greater than the first height.

Abstract: A method includes determining a rate of resource occupancy of a constituent stage of an unbalanced instruction pipeline implemented in a processor through profiling an instruction code. The method also includes performing data processing at a maximum throughput at an optimum clock frequency based on the rate of resource occupancy.

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract: A method of quantization matrix compression in a video encoder is provided that includes preprocessing a quantization matrix by performing at least one selected from down-sampling the quantization matrix and imposing 135 degree symmetry on the quantization matrix, performing zigzag scanning on the pre-processed quantization matrix to generate a one dimensional (1D) sequence, predicting the 1D sequence to generate a residual 1D sequence, and coding the residual 1D sequence using kth order exp-Golomb coding to generate a compressed quantization matrix, wherein k?0.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

Abstract: A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.

Abstract: Apparatus and methods separate the functions of light emission, heat dissipation, and power conversion in LED lighting. Doing so may facilitate cost-effective LED lighting and enable the conversion of existing incandescent lamps to LED service. An LED light bulb includes a thermal path from LED dies to a thermal transfer contact having an externally available surface. The LED light bulb and an incandescent lamp adapter are consumer-installable in an incandescent lamp. A heat spreader component of the lamp adapter contacts the thermal transfer contact of the LED light bulb to dissipate heat originating at the LED dies. A lamp adaptable LED power supply plugs into a standard AC power outlet and includes a receptacle to accept insertion of a lamp cord plug to deliver power to the LED light bulb. A lock-in safety device prevents retraction of the lamp cord plug from the LED power supply once inserted.

Abstract: Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method performed by a PLC device, such as a PLC meter, may include identifying at least one bootstrapping agent and a personal area network (PAN) identifier for one or more networks that are operating within a personal operating space of the PLC device. The device selects a target bootstrapping agent to use for the join process with a target network. The target bootstrapping agent may be selected from a list of bootstrapping agents associated with the target PAN identifier. If the attempt to join the target network fails, then the device further determines if other bootstrapping agents are associated with the target PAN identifier. The device selects an alternate target bootstrapping agent from the other bootstrapping agents that are associated with the target PAN identifier and reattempts the join process.

Abstract: In the present disclosure, an error in the velocity and position computed from a three dimensional IMU measurement is reduced confined by computing an auxiliary speed in a drive direction of a vehicle from an angular velocity measurement and a lateral acceleration measurement. The auxiliary speed is then compared with the speed computed from the acceleration measurement. The auxiliary speed is provided as the speed of the vehicle mounted with the IMU when the absolute difference between the auxiliary speed and the speed computed from the acceleration measurement in the drive direction is above a threshold. The auxiliary speed is computed when the vehicle is detected to be in a curved motion. According to another aspect of the present disclosure, the bias errors are determined when the vehicle is in a steady state, at rest or in a straight line motion. The bias errors are used to obtain the accurate auxiliary measurement.