Abstract: A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying and using redundant information from the image (motion values and edge directions), this scan rate converter is able to perform the tasks of film-mode detection, motion-adaptive scan rate conversion, and content-dependent video noise reduction. Adaptive video noise reduction is incorporated in the process where temporal noise reduction is performed on the still parts of the image, thus preserving high detail spatial information, and data-adaptive spatial noise reduction is performed on the moving parts of the image. A low-pass filter is used in flat fields to smooth out Gaussian noise and a direction-dependent median filter is used in the presence of impulsive noise or an edge. Therefore, the selected spatial filter is optimized for the particular pixel that is being processed to maintain crisp edges.

Abstract: Embodiments of the present disclosure provide a feedback encoder, a feedback decoder and methods of operating the same. The feedback encoder, for use with user equipment, includes an encoding module configured to provide a rank indicator that is separately reportable from a related selection of at least one of a channel quality indicator and a preceding matrix indicator for the user equipment. The feedback encoder also includes a transmit module configured to transmit the rank indicator and the related selection. The feedback decoder, for use with a base station, includes a receive module configured to receive a rank indicator that is separately reportable from a related selection of at least one of a channel quality indicator and a preceding matrix indicator for user equipment. The feedback decoder also includes a decoding module configured to decode the rank indicator and the related selection for the base station.

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.

Abstract: A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting anchors. The resonant frequency is increased by adding a material over the reduced area to stiffen the connection between the torsional hinges and the support anchors.

Abstract: There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections.

Abstract: A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

Abstract: A spatial light modulator is disclosed, along with a method for making such a modulator that comprises an array of micromirror devices. The center-to-center distance and the gap between adjacent micromirror devices are determined corresponding to the light source being used so as to optimize optical efficiency and performance quality. The micromirror device comprises a hinge support formed on a substrate and a hinge that is held by the hinge support. A mirror plate is connected to the hinge via a contact, and the distance between the mirror plate and the hinge is determined according to desired maximum rotation angle of the mirror plate, the optimum gap and pitch between the adjacent micromirrors. In a method of fabricating such spatial light modulator, one sacrificial layer is deposited on a substrate followed by forming the mirror plates, and another sacrificial layer is deposited on the mirror plates followed by forming the hinge supports.

Abstract: This invention provides a battery protecting circuit where even if the battery voltage falls nearly to zero volts due to overdischarge or the like while an NMOS transistor set in the power feeding path on the side of the positive electrode of the battery is turned ON/OFF, it is still possible to charge the battery by a constant charging current in a stable way. When the voltage of battery B1 has not reached the voltage needed for generating the driving voltage of NMOS transistors Q1, Q2 in drives 111, 112, the boosting operation of drives 111, 112 is stopped, and PMOS transistor Q3 inserted in a power feeding path different from that of said transistors is turned ON by driver 113. In driver 113, by clamping voltage VDD generated in the power feeding path of PMOS transistor Q3 to a voltage lower than it, driving voltage ZVO of PMOS transistor Q3 is generated without performing a boosting operation.

Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.

Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).

Abstract: In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected value or a second digitized signal. A comparator is coupled to the first and the second buffer/register to provide the result of a comparison. In this manner, the central processing unit is not involved in the comparison testing procedure.

Abstract: Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the photolithographic mask is operable to pattern a wafer pattern for a semiconductor wafer. Placement of sub-resolution assist features for the main features is estimated. The following is repeated for one or more iterations: correcting the main features using a wafer pattern model operable to estimate the wafer pattern; evaluating the sub-resolution assist features according to the wafer pattern model; and modifying at least one sub-resolution assist feature in accordance with the evaluation.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

Abstract: According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor device, receiving fail data on the semiconductor device, determining a solution model for the semiconductor device based on the fail data, storing the solution model, performing subsequent testing on the semiconductor device, and comparing a result of the subsequent testing to the solution model.

Abstract: A sigma-delta modulator includes a discrete time circuit that receives a digital feedback signal and an input signal, where the input signal includes information and one or more analog input currents. The discrete time circuit converts the digital feedback signal into an analog feedback signal during a first discrete time and sums the analog feedback signal and the one or more analog input currents during a second discrete time to yield one or more summed signals. A continuous time circuit includes passive elements, is coupled to the discrete time circuit, and operates to filter the one or more summed signals using a first-order filter and a second-order filter in order to generate one or more filtered signals. A quantizer is coupled to the continuous time circuit and generates the digital signal using the one or more filtered signals, where the digital signal comprising the information.

Abstract: A method of monitoring a light integrator of a photolithography system, wherein the photolithography system comprises a light source for illuminating different fields of a photosensitive layer and a light integrator for measuring the actual exposure doses of the illuminated fields, comprises the step of illuminating different fields of the photosensitive layer in succession. In each illumination step the actual exposure dose is measured by means of the light integrator, the actual exposure time (actualTime) is controlled so that the actual exposure dose to which a field of the photosensitive layer is exposed corresponds to a desired exposure dose, and the actual exposure time (actualTime) is fed to a monitoring system for in-line monitoring the light integrator during illumination of the fields.

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).