Patents Assigned to Texas Instruments
  • Patent number: 7432841
    Abstract: A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A second, coupled multi-stage delta-sigma modulator quantizes less significant bits of the input signal, wherein a first quantization stage is coupled to the first quantization error signal to quantize the next most significant bits of the input signal and produce a second quantization error signal. A second quantization stage is coupled to the second quantization error signal to quantize the least significant bits of the input signal and produce a third quantization error signal. A noise-shaping filter is coupled to the third quantization error signal, the output of which is subtracted from the first quantization error signal to produce said input of the first quantization stage.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Martin Kithinji Kinyua
  • Patent number: 7432572
    Abstract: The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate, where the MEMS device has a sacrificial layer over components formed therein. The method also includes coupling an assembly lid to the assembly substrate and over the MEMS device to create an interior of the MEMS assembly housing the MEMS device, whereby the coupling maintains an opening to the interior of the MEMS assembly. Furthermore, the method includes removing the sacrificial layer through the opening. A MEMS assembly constructed according to a process of the present invention is also disclosed.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Joshua Malone
  • Patent number: 7434021
    Abstract: A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain
  • Patent number: 7433984
    Abstract: A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sumit Das, Kevin Main, Roy D. Wojciechowski
  • Patent number: 7434029
    Abstract: A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instruction. If there are less than a threshold number of consecutive supported instructions before the next unsupported instruction, the second processor loads the instructions in the first processor for execution so that the first processor does not fetch the instructions. If there are more than a threshold number of consecutive supported instructions before the next unsupported instruction, the first processor fetches and executes those instructions.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre
  • Patent number: 7432566
    Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: October 7, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Mark R. Visokay
  • Publication number: 20080237865
    Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Maria Wang, Erika Leigh Shoemaker, Mary Roby, Stuart Jacobsen
  • Publication number: 20080237745
    Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.
    Type: Application
    Filed: May 1, 2008
    Publication date: October 2, 2008
  • Publication number: 20080240081
    Abstract: In a method, system and apparatus for providing rules-based restriction of incoming calls, a network entity such as a call manager receives a call request from a caller to setup a call to the client. The call manager includes a database including a client profile for the client, the client profile including identification data for the client and one or more client-defined conditions for accepting calls. The call manager also includes a processor coupled to the database that is configured to: query the database to obtain the client profile for the client in response to the call request received from the caller; determine if the call request from the caller satisfies the one or more client-defined conditions; and reject the call request if the call request is determined not to satisfy the one or more client-defined conditions.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventor: Manoj Sindhwani
  • Publication number: 20080242007
    Abstract: The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) over a substrate (310), and then forming a layer of material (510) over the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445). This method further includes selectively etching portions of the layer of material (510) based upon a density or size of the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) located thereunder, and then polishing remaining portions of the layer of material (510).
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Kyle Hunt, Neel Bhatt, Asadd M. Hosein, Brian L. Vialpando, William R. Morrison
  • Publication number: 20080242072
    Abstract: A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Jinhan Choi, Hyesook Hong, Donald S. Miles
  • Publication number: 20080242089
    Abstract: A method of manufacturing a semiconductor device. A first thickness of a copper layer located over a semiconductor substrate is removed by chemical-mechanical polishing (CMP) on a first platen using a first polishing slurry. The copper layer is located over a barrier layer. A remaining thickness of the copper layer is removed on a second platen using a second polishing slurry. A portion of the barrier layer on the second platen is removed using a third polishing slurry. The third polishing slurry has a substantially different composition from the second polishing slurry.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Brian E. Zinn, Rashmi Patil
  • Publication number: 20080242114
    Abstract: A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing ambient.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Manuel Quevedo-Lopez, Husam Alshareef
  • Patent number: 7429524
    Abstract: The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one aspect, the method of manufacturing a transistor device includes providing a gate structure (140) over a substrate (110). An insulating layer (310) is formed over the gate structure (140), and openings (710) to the substrate (110) are formed therein, thereby removing a portion of the gate structure (140). The openings (710) are filled with a conductor (1410), thereby forming an interconnect (1510).
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: September 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Marshall, Tito Gelsomini, Harvey Edd Davis
  • Patent number: 7429895
    Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Prakash Easwaran, Anant Shankar Kamath, Rupak Ghayal, Birman Chattopadhyay, Gopal Krishna Nayak, Sameer Raghavendra Joshi, Mithun Guddethota Neelakant, Subhash Yekanath Pai, Shivaprakash Halagur
  • Patent number: 7430072
    Abstract: System and method for maximizing image quality by eliminating vias on a reflective surface. A preferred embodiment comprises depositing a first portion of a mirror surface over a support surface, applying a protective coating on the mirror surface, and then inverting the via. The preferred embodiment also comprises removing a portion of the inverted via and then depositing a second portion of the mirror surface. The remaining portion of the inverted via fills the via and provides a level surface for the depositing of the second portion of the mirror surface, reducing the amount of light scattered by the via.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: September 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Ronald Charles Roth, Timothy Joseph Hogan, Lucius Sherwin
  • Patent number: 7429517
    Abstract: A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures (120), (130) are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: September 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiqiang Wu, Haowen Bu
  • Patent number: 7430141
    Abstract: A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data signals prior to sampling. A delay is increased for an individual data signal if it transitions prior to the delayed strobe signal and the delay is decreased if the data signal transitions after the delayed strobe signal.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: September 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Andrea Bonelli
  • Publication number: 20080230846
    Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 25, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Yaw S. Obeng, Juanita DeLoach, Freidoon Mehrad
  • Publication number: 20080232146
    Abstract: Various embodiments of the present invention provide rectifier controllers, power supplies and methods for operating such. As one example, a rectifier controller circuit is disclosed that includes a transistor, a phase locked loop circuit, a period counter and a combinational logic circuit. One leg of the transistor is electrically coupled to a switch node of a power supply, and is in parallel to a diode of the power supply. The phase locked loop circuit receives a signal representing a voltage at the switch node, and is operable to synchronize to a period of the signal representing the voltage at the switch node. The period counter divides the period of the signal representing the voltage at the switch node into segments.
    Type: Application
    Filed: January 23, 2008
    Publication date: September 25, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Ted Thomas, Roman Korsunsky, Michael G. Amaro