Abstract: Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless scanning so as to receive wireless signals from one or more access points from among a plurality of access points positioned at plurality of locations, respectively at one or more floors from among a plurality of floors within the multi-floor environment. A first set of RSSI measurements is computed corresponding to the wireless signals. Absolute floor location information is determined based on the first set of RSSI measurements and a pre-defined objective function. The pre-defined objective function is configured to maximize a probability of a user being located at a floor so as to receive the wireless signals. A user floor location is determined based on the absolute floor location information. The user location is estimated at least in part based on the user floor location.

Abstract: A location or position sensor apparatus and sensor systems are presented, in which individual location sensors store and wirelessly exchange orbital information, soft demodulation information, position and time of day information, and the sensors share decoding and computation tasks related to acquiring and tracking navigation satellites to conserve power and to facilitate determination of sensor positions.

Abstract: A circuit includes an input channel array that includes a plurality of channels to receive a plurality of input signals and generate a plurality of channel output signals. A processor to processes the plurality of channel output signals from the input channel array. The processor and the input channel array are configured to operate in a sleep mode when all of the analog input signals are inactive or an active mode when at least one of the analog input signals is active. A secondary channel samples the plurality of input signals and generates a secondary output signal indicative of activity for at least one of the input signals. A secondary channel detector determines a level of signal activity for any of the input signals during the sleep mode based on the secondary output signal.

Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

Abstract: A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art.

Abstract: A method of caching reference data in a reference data cache is provided that includes receiving an address of a reference data block in the reference data cache, wherein the address includes an x coordinate and a y coordinate of the reference data block in a reference block of pixels and a reference block identifier specifying which of a plurality of reference blocks of pixels includes the reference data block, computing an index of a set of cache lines in the reference data cache using bits from the x coordinate and bits from the y coordinate, using the index and a tag comprising the reference block identifier to determine whether the reference data block is in the set of cache lines, and retrieving the reference data block from reference data storage when the reference data block is not in the set of cache lines.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

Abstract: A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold.

Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.

Abstract: A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating beacon periods. The position of the beacon signal shifts within each beacon period based upon a predetermined pseudo-random sequence. The beacon signal includes data identifying the current beacon shift sequence and the current phase of the sequence. Neighboring hubs independently or jointly determine and broadcast their own beacon shift sequences and phases for their respective networks from a predetermined list. Nodes connected with the network hubs are assigned allocation intervals having a start time that is set relative to the beacon signal. The start time and duration of the allocation interval wraps around the beacon period if the allocation-interval would otherwise start or continue in a next beacon period.

Abstract: A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.

Abstract: A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of parameters (FDPD) and a second set of parameters (CDPD) at a first time (904). The first set of parameters is updated at a second time (914). The second set of parameters is updated separately from the first set of parameters at a third time (920).

Abstract: An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Abstract: Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels on at least one area of the EPD are driven individually. The EPD has a second operating format, wherein a plurality of pixels constituting at least one area of the EPD are driven simultaneously. Both the first operating format and the second operating format are performable simultaneously on the EPD.

Abstract: A device with an autonomous sleep characteristic, which is in communication with a host, is described. The device includes one or more communication subsystems. Each communication subsystem maintains a sleep activity indicator that indicates whether a corresponding communication subsystem is allowed to go to sleep. Each communication subsystem can autonomously enter a sleep state, when its sleep activity indicator indicates that the corresponding communication subsystem is, in fact, allowed to go to sleep. The device also includes a controller. The controller has a block memory which stores data written to the device from the host. The controller further includes a sleep state indicator that indicates a sleep state of each communication subsystem.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

Abstract: A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.

Abstract: Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.