Patents Assigned to Texas Instruments
  • TAP with commandable data register control router and routing circuit
    Patent number: 9121905
    Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Detecting wave gestures near an illuminated surface
    Patent number: 9122354
    Abstract: A method for wave gesture detection performed by a touch processor in an optical touch detection system is provided. The method includes receiving a sequence of images of an illuminated surface comprised in the optical touch detection system, wherein the images are captured by a camera comprised in the optical touch detection system, detecting a wave gesture performed in front of the illuminated surface by analyzing the sequence of images, and outputting an indication that a wave gesture has been detected.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vinay Sharma
  • Chip to dielectric waveguide interface for sub-millimeter wave communications link
    Patent number: 9123737
    Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Marco Corsi, Siraj Akhtar, Nirmal C. Warke
  • Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates
    Patent number: 9123570
    Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo Pinto, Frank S. Johnson, Benjamin P. McKee, Shaofeng Yu
  • Tap linking module test access port controller with enable input
    Patent number: 9121904
    Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Multiple rank CQI feedback for cellular networks
    Patent number: 9124532
    Abstract: Single user and multiuser MIMO transmission in a cellular network may be performed by a base station (eNB) transmitting either one, two, or more transmission layers. A user equipment (UE) receives a reference symbol from the base station. The UE processes the reference symbol with one or more of a plurality of precoding matrices to form a plurality of channel quality indices (CQI). The UE provides feedback to the eNB comprising one or more feedback CQI selected from the plurality of CQI and one or more precoding matrix indicators (PMI) identifying the one or more precoding matrices used to form each of the one or more feedback CQIs for two or more ranks.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Runhua Chen, Eko Nugroho Onggosanusi
  • LOW-POWER OFFSET-STORED LATCH
    Publication number: 20150244355
    Abstract: A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Mahadevan Venkiteswaran, Rajavelu Thinakaran
  • MECHANICALLY ROBUST SILICON SUBSTRATE HAVING GROUP IIIA-N EPITAXIAL LAYER THEREON
    Publication number: 20150243494
    Abstract: A method of forming an epitaxial article includes growing a crystal of elemental silicon having a minimum boron doping level of 3.2×1018/cm3 using Czochralski process parameters including a crystal growth velocity (pull speed) [V] which is less than (<) an average axial temperature gradient [G]. The crystal is cut into at least one elemental silicon substrate having a surface aligned to a <111> direction; wherein a ratio of vacancies/interstitials in the silicon substrate is less than (<) 1. At least one epitaxial buffer layer is grown on the surface of the silicon substrate, and at least one epitaxial Group IIIA-N layer is grown on the buffer layer(s).
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: MICHAEL LOUIS HAYDEN, THOMAS ANTHONY MCKENNA, RICK L. WISE, SAMEER PENDHARKAR
  • QUANTUM WELL-MODULATED BIPOLAR JUNCTION TRANSISTOR
    Publication number: 20150243648
    Abstract: A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 27, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • INTEGRATED PASSIVE FLIP CHIP PACKAGE
    Publication number: 20150243639
    Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: You Chye How, Siew Kee Lee, Huay Yann Tay
  • BACKGROUND DAC CALIBRATION FOR PIPELINE ADC
    Publication number: 20150244386
    Abstract: A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: MANAR IBRAHIM EL-CHAMMAS
  • LINE RECEIVER CIRCUIT WITH ACTIVE TERMINATION
    Publication number: 20150244363
    Abstract: A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Applicant: Texas Instruments, Inc.
    Inventor: Horia GIUROIU
  • High voltage CMOS with triple gate oxide
    Patent number: 9117687
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Power supply control method for constant current constant power control
    Patent number: 9118239
    Abstract: A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width modulating a switching power supply according to a voltage control loop duty cycle output or a current control loop duty cycle output, in which the controller selectively presets the voltage control loop duty cycle output to a predetermined value before switching from current loop control to voltage loop control and/or inhibits increase in a voltage loop integrator value during current loop control to mitigate voltage overshoot.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shanguang Xu, Zhong Ye
  • Separating Metallic and Semiconductor SWNTS with sinusoidal dipole-inducing magnetic fields
    Patent number: 9114995
    Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Cooper Wainerdi, Robert Reid Doering, Luigi Colombo
  • ASIP with reconfigurable circuitry implementing atomic operations of a PLL
    Patent number: 9116769
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Single sided bit line restore for power reduction
    Patent number: 9117535
    Abstract: A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit (700) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudhir K. Madan, Hugh P. McAdams
  • Use of three-dimensional top-down views for business analytics
    Patent number: 9117106
    Abstract: A method of analyzing a depth image in a digital system is provided that includes detecting a foreground object in a depth image, wherein the depth image is a top-down perspective of a scene, and performing data extraction and classification on the foreground object using depth information in the depth image.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Goksel Dedeoglu, Vinay Sharma
  • Method to extend data retention for flash based storage in a real time device processed on generic semiconductor technology
    Patent number: 9116830
    Abstract: This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory A. North, Thomas A. Fedorko, Thomas Hegedus
  • Alignment to multiple layers
    Patent number: 9117775
    Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas John Aton, Steven Lee Prins, Scott William Jessen