Abstract: An activity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the system includes: (1) a sensor configured to provide a input Bayer pattern array containing amplitudes corresponding to Gr and Gb cells and (2) a processor coupled to the sensor and configured to (2a) compute for at least some of the Gr and Gb cells: activity measures for pluralities of adjacent, same-type cells, green precompensation factors based on the activity measures, averages for the pluralities of adjacent, same-type cells and averages for pluralities of adjacent, opposite-type cells and (2b) use the green precompensation factors, the averages for the pluralities of adjacent, same-type cells and the averages for the pluralities of adjacent, opposite-type cells to form an output Bayer pattern in which the Gr-Gb gain imbalance is reduced.
Abstract: In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
Type:
Application
Filed:
March 23, 2007
Publication date:
September 25, 2008
Applicant:
Texas Instruments Incorporated
Inventors:
Jinhan Choi, Freidoon Mehrad, Frank S. Johnson
Abstract: Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (MS) connected in series with a cascode transistor (MSC), and a differential amplifier (A1) with an inverting input connected to the node between the control transistor and the cascode transistor, a non-inverting input connected to a reference voltage source (VRDS) and an output connected to the gate of the cascode transistor (MSC). The voltage at the output of the differential amplifier (A1) is monitored, and an error condition is determined when the voltage exceeds or drops below a predetermined threshold value. The invention considerably widens the useful operating range, without requiring sophisticated or complex detection circuitry.
Abstract: A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness of the channel pulse response. The resulting interpolator is an adaptive linear filter; and its taps can be adapted with the LMS algorithm. Using this interpolator enables a user to significantly reduce the complexity of the analog clock control circuit. A Gigabit Ethernet receiver that controls the A/D clock by selecting one of several evenly space clock phases, for example, reduced the required number of clock phases from 64 to 16.
Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.
Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).
Abstract: An expert protocol analyzer, which records a protocol exchange between two or more hardware devices on a network or software modules in a multiprogramming environment. To validate a potential fix, the protocol is replayed in a simulated network environment, where a replay unit replaces the endpoint that is not available in the lab, or which in the lab operates with a different timing. The replay unit behaves like one of the two original units of the. Individual messages are adjusted for the local network parameters and are sent with precise delay or timing recorded during the original exchange. This allows the user to recreate the failure scenario in the test lab.
Abstract: A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.
Type:
Grant
Filed:
March 23, 2007
Date of Patent:
September 23, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Robert Bogdan Staszewski, Dirk Leipold, Wei Chen
Abstract: A system and method of removing discrete spurious signals in cable broadband environments as well as in other RF environments employs either non-decision directed or decision directed techniques in order to remove the discrete spurious signals. The non-decision directed technique converts the signal of interest such that the spurious signal's frequency is approximately zero, filters out the converted spurious signal, and then reconverts the signal of interest back to its original location. The decision directed technique employs a decision mechanism such as a slicer to regenerate a spurious signal that is subtracted from the signal of interest containing the actual spurious signal such that the actual spurious signal is removed from the signal of interest.
Type:
Grant
Filed:
August 31, 2004
Date of Patent:
September 23, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Nir Sasson, Raanan Yechezkel, Uri Garbi, Alon Elhanati, Naftali Sommer
Abstract: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode 200, and integrated circuit 800 have includes a semiconductor device 805 having the described source/drain electrodes 810.
Type:
Grant
Filed:
August 7, 2006
Date of Patent:
September 23, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Majid M. Mansoori, Christoph A. Wasshuber
Abstract: Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present invention relates to a control system for a power supply. The system includes a bias generator that provides a bias signal operative to charge a storage device based on a control signal. During a low power mode, a control system provides the control signal with a predetermined duty cycle that is functionally related to a storage capacity of the storage device.
Abstract: Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.
Abstract: When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal. The interrupt service routine code flush sync marker identifies the absolute program counter address at the time of the generation of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal and relates the INTERRUPT SERVICE ROUTINE CODE FLUSH signal sync marker to a timing trace stream. The INTERRUPT SERVICE ROUTINE CODE FLUSH signal is generated at the transition between the interrupt service routine (secondary) code instructions being removed from the pipeline flattener and the program (primary) code instructions being removed from the pipeline flattener.
Type:
Grant
Filed:
December 5, 2003
Date of Patent:
September 23, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Gary L. Swoboda, Bryan Thome, Manisha Agarwala
Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).
Type:
Grant
Filed:
July 25, 2007
Date of Patent:
September 16, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Zhijian Lu, Thomas M. Wolf, Scott W. Jessen
Abstract: A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.
Abstract: Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.
Abstract: A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.
Type:
Grant
Filed:
June 30, 2006
Date of Patent:
September 16, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Lars Risbo, Asit Shankar, Josey George Angilivelil
Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.
Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.