Abstract: A sigma-delta modulator includes a discrete time circuit that receives a digital feedback signal and an input signal, where the input signal includes information and one or more analog input currents. The discrete time circuit converts the digital feedback signal into an analog feedback signal during a first discrete time and sums the analog feedback signal and the one or more analog input currents during a second discrete time to yield one or more summed signals. A continuous time circuit includes passive elements, is coupled to the discrete time circuit, and operates to filter the one or more summed signals using a first-order filter and a second-order filter in order to generate one or more filtered signals. A quantizer is coupled to the continuous time circuit and generates the digital signal using the one or more filtered signals, where the digital signal comprising the information.

Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.

Abstract: In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In making a comparison with a predetermined value, a second buffer/register stores either a preselected value or a second digitized signal. A comparator is coupled to the first and the second buffer/register to provide the result of a comparison. In this manner, the central processing unit is not involved in the comparison testing procedure.

Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).

Abstract: A spatial light modulator is disclosed, along with a method for making such a modulator that comprises an array of micromirror devices. The center-to-center distance and the gap between adjacent micromirror devices are determined corresponding to the light source being used so as to optimize optical efficiency and performance quality. The micromirror device comprises a hinge support formed on a substrate and a hinge that is held by the hinge support. A mirror plate is connected to the hinge via a contact, and the distance between the mirror plate and the hinge is determined according to desired maximum rotation angle of the mirror plate, the optimum gap and pitch between the adjacent micromirrors. In a method of fabricating such spatial light modulator, one sacrificial layer is deposited on a substrate followed by forming the mirror plates, and another sacrificial layer is deposited on the mirror plates followed by forming the hinge supports.

Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.

Abstract: Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the photolithographic mask is operable to pattern a wafer pattern for a semiconductor wafer. Placement of sub-resolution assist features for the main features is estimated. The following is repeated for one or more iterations: correcting the main features using a wafer pattern model operable to estimate the wafer pattern; evaluating the sub-resolution assist features according to the wafer pattern model; and modifying at least one sub-resolution assist feature in accordance with the evaluation.

Abstract: There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: A method of monitoring a light integrator of a photolithography system, wherein the photolithography system comprises a light source for illuminating different fields of a photosensitive layer and a light integrator for measuring the actual exposure doses of the illuminated fields, comprises the step of illuminating different fields of the photosensitive layer in succession. In each illumination step the actual exposure dose is measured by means of the light integrator, the actual exposure time (actualTime) is controlled so that the actual exposure dose to which a field of the photosensitive layer is exposed corresponds to a desired exposure dose, and the actual exposure time (actualTime) is fed to a monitoring system for in-line monitoring the light integrator during illumination of the fields.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: Provided, in one embodiment, is a method for manufacturing a resistive structure. This method, without limitation, includes forming a substrate, and forming a tantalum-aluminum-nitride resistive layer over the substrate. Moreover, a bulk resistivity of the tantalum-aluminum-nitride resistive layer may be adjusted by varying at least one deposition condition selected from the group consisting of a flow rate ratio of nitrogen to argon, power, pressure, temperature and radio frequency (RF) bias voltage.

Abstract: Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include purging the deposition chamber having been subjected to the plasma clean with an inert gas, and pumping the deposition chamber having been subjected to the plasma clean.

Abstract: Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100, among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor device 100 may include a dynamic defect 125 located within the lattice structure and proximate the implanted precipitate region 120, such that the implanted precipitate region 120 affects a position of the dynamic defect 125 within the lattice structure. Located over the substrate 110 in the aforementioned semiconductor device 100 is a gate structure 160.

Abstract: Systems and methods for detecting a short in an electrical distribution system are disclosed. In one embodiment, a determination is made as to whether a short condition is satisfied based on a change in a voltage in a wire harness coupled to a first side of a switch. The determination of whether a short exists is made in response to determining whether the short condition has been satisfied for at least a threshold time. The threshold time is dependent on a change in a voltage of the wire harness coupled to a second side of the switch.

Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).

Abstract: Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

Abstract: In one aspect, the present invention provides a system and method for selecting precursor equalizer coefficients and a serializer deserializer (SERDES) incorporating the system or the method. In one embodiment, the system includes: (1) a cost definer configured to generate an eye height cost function based on continuous-time channel and crosstalk symbol responses pertaining to a particular serial link and (2) a cost evaluator associated with the cost definer and configured to evaluate the eye height cost function based on a particular criterion thereby to produce coefficients for a precursor equalizer to be applied with respect to the particular serial link.