Abstract: A method for network coding includes generating a message matrix, where each column of the message matrix corresponds to one of K message packets and each element in a column of the message matrix corresponds to one of the symbols of the corresponding message packet. The method further includes generating a network code matrix to map the K message packets to N encoded packets, where any combination of K columns of the network code matrix is linearly independent and N is greater than K. The method also includes multiplying the message matrix by the network code matrix to generate a transmission matrix, where each column of the transmission matrix corresponds to an encoded packet for wireless transmission.

Abstract: A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding.

Abstract: An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.

Abstract: Embodiments of the invention provide a system and method to improve the performance of a GNSS receiver using antenna switching. The system has a plurality of antennas and at least one radio frequency RF chain. There are fewer RF chain(s) than antennas. A receiver processes a plurality of signals sent by a plurality of transmitters. The system also includes antenna switches and switch controller. The method includes processing signals from a plurality of satellite vehicles SVs using an antenna selected from a plurality of antennas.

Abstract: Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

Abstract: Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A common header segment is encoded alone, and an embedded header segment is encoded with payload data. The interleaver operates on blocks having a size based upon a total number of input bits in an FEC codeword block, a total number of bits loaded on symbols that span a half mains cycle, or a maximum fragment size of 3072 bits. The blocks may be repeated before interleaving. Each block and its repetitions may be interleaved together, such as for header data, or each block and repetition may be interleaved separately, such as for payload data. Cyclic padding may be used on each block to create an integer number of symbols for transmission.

Abstract: A method includes, for a device and at each of a plurality of sampling frequencies, measuring a parameter of the device to generate a plurality of signals and each signal represents a time series of values of the parameter. Further, the method includes for each of the plurality of signals, identifying at least two stable states in the time series for each signal. Still further, the method includes determining a time constant associated with each stable state of each signal, determining a relationship between the time constants of each stable state and sampling frequency, and computing a final time constant value for each steady state by computing a derivative of the time constants as a function of sampling frequency relationship and comparing the derivative to a threshold.

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract: A method for network coding using a near-maximum distance separable linear network code includes generating a message matrix where each column of the message matrix corresponds to one of K message packets and each element in a column of the message matrix corresponds to one of the symbols of the corresponding message packet. The method also includes generating a network code matrix to map the K message packets to N encoded packets, where any combination of K+1 columns of the network code contains at least K columns that are linearly independent. Further, the method includes multiplying the message matrix by the network code matrix to generate a transmission matrix, where each column of the transmission matrix corresponds to an encoded packet for wireless transmission.

Abstract: Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

Abstract: Embodiments of the present disclosure provide a base station sub-system, a method of allocating random access configurations and a method of downlink signaling of random access configurations. In one embodiment, the base station sub-system is for use in a wireless communication system and includes an allocator configured to allocate random access configurations having a plurality of time slots that use a single frequency resource. Additionally, the base station sub-system also includes a transmitter configured to signal at least one index of the random access configurations and a random access receiver balancing in time the processing load of the random access detection of different cells served by the base station.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.

Abstract: The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: A method and system for compressing an audio signal. The method includes receiving a segment of an audio signal and selectively disabling noise suppression for the received segment. The segment is filtered in a noise-suppression module if noise suppression is not disabled. The method also includes calculating an autocorrelation coefficient and an LSP coefficient, predicting a short-term coefficient and long-term coefficients according to the LSP coefficient and calculating one or more bandwidth-expanded correlation coefficients. Further, the method includes determining the type of packet in which to encode the segment. An encoding rate is selected from among a full rate encode, a half-rate encode, and an eight-rate encode if noise suppression is not disabled. An encoding rate is selected from among a full rate encode and a half-rate encode if noise suppression is disabled. Furthermore, the segment is formed into a packet of the determined type and selected rate.

Abstract: A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.

Abstract: A method of generating an integrated circuit with a double patterning technology (DPT) compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.

Abstract: An apparatus for rotating a load about a predetermined rotation axis of the apparatus. The apparatus includes a rotatable shaft having a central longitudinal axis; a turntable fixedly mounted on the rotatable shaft; an annular centering surface; and a stud member positioned opposite the annular centering surface. Either the annular centering surface or the stud member is affixed to the turntable. The annular centering surface and the stud member are adapted to co-act to maintain the central longitudinal axis of the rotatable shaft in alignment with the predetermined rotation axis of the apparatus.

Abstract: An electronic device includes a power stage, a switch and a controller. Power is transferred from an input through the power stage to an output. The switch turns on and off a current provided to the power stage for transferring the power. The controller turns on and off the switch. During a low-load mode, the controller causes the switch to operate with a constant on-time control.

Abstract: A circuit includes a comparator that monitors a transient with respect to a predetermined threshold at the output of a voltage regulator and generates a compensation signal if the transient exceeds the predetermined threshold. A dynamic current pull-down block is triggered from the compensation signal of the comparator and operative with an output stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch.

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.