Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

Abstract: A method of monitoring a light integrator of a photolithography system, wherein the photolithography system comprises a light source for illuminating different fields of a photosensitive layer and a light integrator for measuring the actual exposure doses of the illuminated fields, comprises the step of illuminating different fields of the photosensitive layer in succession. In each illumination step the actual exposure dose is measured by means of the light integrator, the actual exposure time (actualTime) is controlled so that the actual exposure dose to which a field of the photosensitive layer is exposed corresponds to a desired exposure dose, and the actual exposure time (actualTime) is fed to a monitoring system for in-line monitoring the light integrator during illumination of the fields.

Abstract: Provided, in one embodiment, is a method for manufacturing a resistive structure. This method, without limitation, includes forming a substrate, and forming a tantalum-aluminum-nitride resistive layer over the substrate. Moreover, a bulk resistivity of the tantalum-aluminum-nitride resistive layer may be adjusted by varying at least one deposition condition selected from the group consisting of a flow rate ratio of nitrogen to argon, power, pressure, temperature and radio frequency (RF) bias voltage.

Abstract: Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include purging the deposition chamber having been subjected to the plasma clean with an inert gas, and pumping the deposition chamber having been subjected to the plasma clean.

Abstract: Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100, among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor device 100 may include a dynamic defect 125 located within the lattice structure and proximate the implanted precipitate region 120, such that the implanted precipitate region 120 affects a position of the dynamic defect 125 within the lattice structure. Located over the substrate 110 in the aforementioned semiconductor device 100 is a gate structure 160.

Abstract: Systems and methods for detecting a short in an electrical distribution system are disclosed. In one embodiment, a determination is made as to whether a short condition is satisfied based on a change in a voltage in a wire harness coupled to a first side of a switch. The determination of whether a short exists is made in response to determining whether the short condition has been satisfied for at least a threshold time. The threshold time is dependent on a change in a voltage of the wire harness coupled to a second side of the switch.

Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).

Abstract: Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

Abstract: In one aspect, the present invention provides a system and method for selecting precursor equalizer coefficients and a serializer deserializer (SERDES) incorporating the system or the method. In one embodiment, the system includes: (1) a cost definer configured to generate an eye height cost function based on continuous-time channel and crosstalk symbol responses pertaining to a particular serial link and (2) a cost evaluator associated with the cost definer and configured to evaluate the eye height cost function based on a particular criterion thereby to produce coefficients for a precursor equalizer to be applied with respect to the particular serial link.

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: The objective of the invention is to provide a type of data transfer system for generating plural timing signals, etc. for any device. Data transfer system A transfers plural data blocks received with one input channel to plural output channels. Each data block contains data, destination identification indicating the output channel to be transferred to, first timing information, and second timing information. System A has selection output unit 32. As a result, each received data block is sent to one output channel indicated by the destination identification in the data block. Also, system A has first timing control unit 300 and second timing control unit 302. As a result, the received data blocks are transferred at a first relative timing indicated by the first timing information or a second relative timing indicated by the second timing information with respect to a time standard.

Abstract: The invention provides a method for quantifying over-etch of a conductive feature. In one embodiment, this method includes forming a conductive feature over a substrate, the conductive feature having a sheet resistance test structure associated therewith, the sheet resistance test structure having a first sheet resistance value. This method may further include etching the conductive feature and the sheet resistance test structure using a common etch process, obtaining a second sheet resistance value of the sheet resistance test structure after the etching, and quantifying an amount of over-etch into the conductive feature using the first and second sheet resistance values.

Abstract: The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.

Abstract: A hysteretic DC/DC converter is proposed that operates at a high switching frequency without producing undesired pulse bursts at the output. The converter has a converter power stage with a supply voltage input, a controlled voltage output and an enable input. A comparator has a reference voltage input, a feedback input and an output, and a gating circuit connected between the output of the comparator and the enabling input of the converter power stage. The gating circuit inhibits as a function of load requirements the propagation of enabling pulses from the output of the comparator to the enabling input of the converter power stage. By gating the output of the comparator in a way to separate the output from the enabling input of the converter power stage immediately after the start of each conversion pulse, the generation of further pulses immediately after each conversion pulse is prevented, thereby keeping the output voltage ripple low.

Abstract: A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter for use in a base station of an OFDMA system and includes a primary module configured to provide a primary synchronization signal that furnishes a partial cell identity. Additionally, the transmitter also includes a secondary module configured to provide a secondary synchronization signal that furnishes a cell identity group and one or more cell-specific parameters based on using a two-segment secondary synchronization sequence. The transmitter further includes a transmit module configured to transmit the primary and secondary synchronization signals.

Abstract: A proximity-based system for, and method of, reducing Gr-Gb gain imbalance and a digital camera incorporating the system or the method. In one embodiment, the system includes: (1) a sensor configured to provide a input Bayer pattern array containing amplitudes corresponding to Gr and Gb cells and (2) a processor coupled to the sensor and configured to (2a) compute for at least some of the Gr and Gb cells: closeness measures for pluralities of adjacent, same-type cells, weights for pluralities of adjacent, opposite-type cells based on the closeness measures and weighted averages of the pluralities of the adjacent, opposite-type cells based on the weights and (2b) use the weighted averages to form an output Bayer pattern in which the Gr-Gb gain imbalance is reduced.