Abstract: A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: System and method for reducing failures due to hinge memory in a microdisplay display system. A preferred embodiment includes setting the state of each micromirror in a digital micromirror device based on an image being displayed, recording a usage history for the micromirrors, and providing a sequence of states to each micromirror when the display system is in an inactive mode. The sequence of states provided to a micromirror is based on the micromirror's usage history. The operation of the micromirrors while a display system containing the digital micromirror device is not in active use can help to reverse or eliminate hinge memory, thereby extending the lifetime of the digital micromirror device.

Abstract: A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).

Abstract: In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess in a portion of the source region and a second recess in a portion of the drain region. The method also includes activating the dopants in the source region and the drain region by heating the active regions and depositing a semiconductor material in the first recess and the second recess after activating the dopants in the source region and the drain region.

Abstract: To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave oscillating circuit has two triangular wave generating circuits 10A and 10B for generating two phased triangular waves A and B with phases opposite each other, a middle point potential fixing element 20 that always fixes the middle point potential of the output voltage A and B of the two triangular wave generating circuits 10A and 10B at a fixed value, and a mode switching element 30 that instantly switches the output voltage generation mode (up-slope waveform mode/down-slope waveform mode) in the two triangular wave generating circuits 10A and 10B at a preset reference wave crest value level.

Abstract: A system and method facilitate estimating noise in a received signal. The received signal is formed of a plurality of tones, such as training tones and data tones. Noise is estimated at the training tones, which generally comprise a lesser number of the tones in the received signal than the data tones. The estimated noise at the training tones can be employed to facilitate demodulating and/or decoding data tones in the received signal. In one aspect, the estimated training tone noise can be utilized by a beamformer.

Abstract: A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.

Abstract: Soft estimate normalization for weighted multiantenna high-order modulation data channel together with separate antenna pilot channels using averaging in first time slots of a transmission time interval with corrections for subsequent time slots.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located over a substrate (110), and a silicided gate electrode (150) located over the gate oxide (140), wherein the silicided gate electrode (150) includes a first metal and a second metal.

Abstract: An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic properties and a second transistor of a second technology type having a second group of the intrinsic properties, at least one of the intrinsic properties of the second group being substantially different than a corresponding intrinsic property of the first group, the second transistor having a first electrode coupled to a supply voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a bias voltage conductor and also coupled to a control electrode and a second electrode of the first transistor. A source of bias current is coupled to the bias voltage conductor and is also coupled to the second electrode of the second transistor. A bias voltage across the composite transistor is produced on the bias voltage conductor to bias a cascode transistor of the first technology type.

Abstract: Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the threshold represents a number of toggles in the corresponding portion. The toggles can include the transitions that would be caused by the logical operation of the combinatorial elements in the IC as well as the transient glitches caused by arrival of input signals at different time points.

Abstract: A semiconductor device (400) with a plastic package (401) having on its surface (401a) a mark (402) identifying the location, where the runner for the molding compound was broken off. The device further exhibits a leadframe with a pad, which has a planar area (403) and a tab (404). The tab is bent at an angle (405) between 120° and 160°, preferably about 135°, towards the planar area and reaches a height (406) over the area. At least portions of the leadframe, including the pad and the tab, are encapsulated by the package; the tab (404) is parallel to the package side (401a) with the mark (402). The device has a semiconductor chip (410) attached to the pad; the thickness (411) of the chip is between 0.5 times and 1.0 times, preferably about 0.7 times, the tab height over the pad.

Abstract: A file system which ensures that some of the (desired) files (“linear files”) are stored in corresponding exclusive blocks (i.e., a block that stores data corresponding to one file only). Due to such a feature, rewriting of data corresponding to other files would not cause data corresponding to linear files to be relocated/rewritten. Such a feature may provide reliable and steady retrieval of data of the corresponding file from a flash memory organized as sectors. According to another aspect, some of the files (“non-linear files”) are stored in non-exclusive blocks (i.e., multiple files can share the same block or the same file can span multiple blocks without contiguity).

Abstract: An architecture for a cascaded digital filters comprises independently programmable controlling registers and independent interpolating factors; a digital to analog converter for converting the digital signals into analog signals with a constant sampling rate which matches with the interpolating factors of the cascaded digital filters. Each filter property (filters order, coefficient symmetry, half-band, and poly-phase) can be programmed independently to support different system requirements and extract maximum throuput from a given hardware. The method of filtering digital signals comprises the steps of determining an interpolation factor of the cascaded digital filters with the lowest number of computations so as to match with the single sampling rate of the digital to analog converter, determining active filters and an interpolation factor of each digital filter in the cascaded digital filters, and determining a mode of operation of the cascaded digital filters.

Abstract: Asynchronous sampling rate converter with input/output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control frequency ratio estimation.

Abstract: A system and method are provided for stopping a quantized signal from a noise-shaper with a significantly reduced inband transient, compared to a traditional random stop of a noise-shaped signal. The noise-shaped signal is stopped at a favorable time controlled by a detector that monitors the noise-shaped signal. The detector indicates the occurrence of a good time to stop the noise-shaper such that the transient due to the stop is minimized in a fashion that substantially reduces the inband disturbance.

Abstract: A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

Abstract: A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM device of the serial cascade arrangement receives a portion of the search word. Each of the CAM devices in the serial cascade arrangement includes a CAM, a plurality of GMAT lines, a dummy match line, and a GMAT interface circuitry. The GMAT interface circuitry facilitates driving the match signals from a substantially previous CAM to a substantially adjacent CAM. The last CAM device is coupled to a match latch and a priority encoder.

Abstract: A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on relatively small-value signals and alternative circuitry for amplifying/processing signals during a condition which otherwise would cause thermal imbalance in the main circuitry. The circuit stage includes switching circuitry for coupling signals in the signal path of the input signal to the main input circuitry during normal small-signal operating conditions and for coupling signals in the signal path of the input signal to the alternative circuitry during the condition which otherwise would cause thermal imbalance in the main circuitry.